Junior Design Verification Engineer for LEO Satellite ASICs

Amazon; Austin (TX); On-site; USD 110,000 - 160,000; Full time

Benefits offered by this job

Health insurance

401(k) matching

Paid time off

Parental leave

RSUs

Job summary

Amazon Kuiper Manufacturing Enterprises LLC in Austin, TX is seeking a verification engineer to define and implement digital chip SOCs for LEO satellite communications and Amazon gateways.

You will develop a state-of-the-art verification environment, write tests, run regressions, and participate in ASIC validation using Verilog/SystemVerilog and UVM. Collaboration with design and system teams is essential to deliver robust modem interfaces and DSP solutions.

Qualifications

• Bachelor's degree in Electrical / Communications Engineering or Computer Science, or related field, or equivalent experience.
• 2+ years in verification preferably in communication systems.
• 2+ years in UVM.

Responsibilities

• Implement a state of the art verification environment to facilitate testing of the RTL against reference Matlab/C models.
• Develop detailed test plans and write tests, run regressions, collect coverage matrices and report progress to the program.
• Participate in the validation of ASIC implementations in Verilog/SystemVerilog.
• Work with the design and communication systems team and participate in system level verification using test benches constructed using UVM.
• Develop a highly automated environment to run regressions that can be used to make builds and maintain organization of the database.

Skills

UVM

Verification

Matlab experience

Education

Bachelor's degree in Electrical / Communications Engineering or Computer Science, or related field, or equivalent experience

Tools

SystemC

Verilog/SystemVerilog

C/Embedded C

Job description

Amazon Kuiper Manufacturing Enterprises LLC in Austin, TX is seeking a verification engineer to define and implement digital chip SOCs for LEO satellite communications and Amazon gateways.

You will develop a state-of-the-art verification environment, write tests, run regressions, and participate in ASIC validation using Verilog/SystemVerilog and UVM. Collaboration with design and system teams is essential to deliver robust modem interfaces and DSP solutions.