Sr. ASIC Design Verification Engineer, Amazon Leo

Anysilicon; Redmond, Northern (WA, KY); Hybrid; USD 140,000 - 230,000; Full time

Job summary

Amazon Kuiper Manufacturing Enterprises LLC in Redmond, WA is seeking a Senior ASIC Design Verification Engineer to join the Leo team focused on digital chip SOCs for low-Earth-orbit satellite communications. You will develop verification environments and validate RTL against Matlab/C models.

The role involves creating automated regression workflows, writing tests, and coordinating with design, systems, and testing teams using UVM, SystemC, and DPI-C to ensure functional correctness of complex

Qualifications

• Bachelor's degree in Electrical or Communications Engineering or related field.
• 7+ years of verification experience, preferably in communication systems.
• 3+ years of experience with UVM, C, SystemC, and scripting.

Responsibilities

• Implement a state-of-the-art verification environment for testing RTL against reference Matlab/C models.
• Develop detailed test plans, write tests, run regressions, and report progress to the program.
• Participate in the validation of ASIC implementations in Verilog/SystemVerilog.
• Conduct formal verification of complex blocks to ensure functional correctness.
• Collaborate with design and communication systems teams for system-level verification using UVM, SystemC, and DPI-C.
• Create a highly automated environment for running regressions and maintaining database organization.

Skills

UVM

C

SystemC

Scripting

Verilog/SystemVerilog

Education

Bachelor's degree in Electrical or Communications Engineering or related field

Master's degree or Ph.D. in Electrical Engineering or related field

Tools

Matlab

DPI-C

Job description

Sr. ASIC Design Verification Engineer, Amazon Leo

Amazon Kuiper Manufacturing Enterprises LLC, Redmond, WA

Job Description:

Amazon Leo is seeking a skilled engineer to join its team focused on developing digital chip SOCs for communication via Low Earth Orbit satellites. This role offers the chance to create innovative wireless solutions that enhance connectivity for various customers, including households, schools, and businesses.

Responsibilities:

• Implement a state-of-the-art verification environment for testing RTL against reference Matlab/C models.
• Develop detailed test plans, write tests, run regressions, and report progress to the program.
• Participate in the validation of ASIC implementations in Verilog/SystemVerilog.
• Conduct formal verification of complex blocks to ensure functional correctness.
• Collaborate with design and communication systems teams for system-level verification using UVM, SystemC, and DPI-C.
• Create a highly automated environment for running regressions and maintaining database organization.

Qualifications:

• Bachelor's degree in Electrical or Communications Engineering or a related field.
• 7+ years of verification experience, preferably in communication systems.
• 3+ years of experience with UVM, C, System C, and scripting.

Skills:

• Master's degree or Ph.D. in Electrical Engineering or related field (preferred).
• 10+ years in digital verification, preferably in communication systems (preferred).
• Familiarity with Matlab and modem design verification (preferred).
• Experience in System C or Matlab model development or DV integration (preferred).
• Knowledge of formal verification techniques (preferred).
• Strong written and verbal communication skills.