Lead ASIC Design Verification Engineer, Amazon Leo

Anysilicon; Sunnyvale, Northern (CA, KY); Hybrid; USD 160,000 - 220,000; Full time

Job summary

Amazon Kuiper Manufacturing Enterprises LLC in Sunnyvale, CA seeks a Lead ASIC Design Verification Engineer to advance digital chip SOC verification for satellite communications.

You will implement verification environments, write tests in C/C++, run regressions, and collaborate across design and systems teams using UVM, SystemC, and DPI-C. The role emphasizes formal verification and automation of regressions for a high-reliability space-grade project.

Qualifications

• 7+ years in verification, preferably in communication systems.
• 5+ years in UVM, C/C++, and scripting.
• Bachelor's degree in Electrical or Communications Engineering or a related field.
• Master's degree or PhD preferred (optional).

Responsibilities

• Implement a verification environment for testing RTL against reference Matlab/C models.
• Develop detailed test plans, write tests, run regressions, and report progress.
• Write tests in C/C++ for execution on embedded CPUs.
• Develop tests for FPGA and emulation platforms.
• Conduct formal verification of complex blocks for functional correctness.
• Collaborate with design and communication systems teams for system-level verification using UVM, SystemC, and DPI-C.
• Create a highly automated environment for running regressions and maintaining database organization.

Skills

UVM

C/C++

SystemC

DPI-C

Matlab familiarity

Formal verification

Education

Bachelor's degree in Electrical/Communications Engineering

Master's or PhD preferred

Tools

UVM

SystemC

DPI-C

Matlab

Job description

Lead ASIC Design Verification Engineer, Amazon Leo

Amazon Kuiper Manufacturing Enterprises LLC, Sunnyvale, CA

Job Description

Amazon Leo is developing a low Earth orbit satellite network aimed at providing reliable internet connectivity to underserved areas. The role involves working on digital chip SOCs for communication systems, focusing on innovative wireless solutions without legacy constraints.

Responsibilities

• Implement a verification environment for testing RTL against reference Matlab/C models.
• Develop detailed test plans, write tests, run regressions, and report progress.
• Write tests in C/C++ for execution on embedded CPUs.
• Develop tests for FPGA and emulation platforms.
• Conduct formal verification of complex blocks for functional correctness.
• Collaborate with design and communication systems teams for system-level verification using UVM, System C, and DPI-C.
• Create a highly automated environment for running regressions and maintaining database organization.

Qualifications

• Bachelor's degree in Electrical or Communications Engineering or a related field.
• 7+ years in verification, preferably in communication systems.
• 5+ years in UVM, C/C++, and scripting.

Skills

• Master's degree or Ph.D. in Electrical Engineering or related field (preferred).
• 10+ years in digital verification, preferably in communication systems (preferred).
• Familiarity with Matlab (preferred).
• Knowledge of formal verification techniques (preferred).
• Strong written and verbal communication skills.

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

Find the Right Semiconductor Partner

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

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