Junior ASIC Formal Verification Engineer

Annapurna Labs; Cupertino (CA); On-site; USD 116,000 - 134,000; Full time

Job summary

Annupurna Labs (U.S.) Inc. is seeking a hardware verification engineer to define and check specifications for critical hardware blocks using formal methods. You will join a world-class pre-silicon design team, working with Verilog/SVA and model checkers to prove compliance with the modeled specification.

The role involves understanding hardware requirements, writing functional descriptions, and leveraging scripting to accelerate proof techniques in a fast-paced AWS hardware ecosystem.

Qualifications

• Bachelor's or Master's degree required or in progress.
• Experience with formal methods in SW/HW design.
• Strong fundamentals in computer architecture.

Responsibilities

• Define and check specifications of critical hardware modules using formal methods.
• Work with a world-class pre-silicon hardware design team on RTL and verification.
• Develop automation/scripts to accelerate proof techniques.

Skills

Formal methods knowledge

Computer architecture

Programming (Python/TCL)

Education

Bachelor's or Master's degree in CS/EE

Tools

JasperGold

VC Formal

RTL Verilog

Job description

Annupurna Labs (U.S.) Inc. is seeking a hardware verification engineer to define and check specifications for critical hardware blocks using formal methods. You will join a world-class pre-silicon design team, working with Verilog/SVA and model checkers to prove compliance with the modeled specification.

The role involves understanding hardware requirements, writing functional descriptions, and leveraging scripting to accelerate proof techniques in a fast-paced AWS hardware ecosystem.