Innovative Wafer Process Integration Engineer

Headway Technologies; Milpitas (CA); On-site; USD 121,000 - 178,000; Full time

Job summary

Headway Technologies in Milpitas, California, is seeking an Integration Engineer to advance prototype wafer processes for new technology programs. You will perform wafer-level characterization, analyze backend performance data, and recommend corrective actions to ensure robust processes.

The role requires a PhD or Master’s in a related field (or equivalent experience) and hands-on semiconductor process experience. Proficiency with JMP and Microsoft Office is expected.

Qualifications

• Bachelor’s degree in Electrical Engineering, Materials Science, or Physics; Master’s or PhD preferred.
• Three years of hands-on experience in process integration or characterization in a semiconductor environment.
• Hands-on experience using JMP or similar analytical application.
• Proficient in Microsoft Office Applications.

Responsibilities

• Develops and delivers process integration and characterization techniques for new technology programs and next generation products.
• Designs and conducts experiments to verify process robustness; analyzes data and performs FMEA to meet product requirements.
• Reviews, monitors, and analyzes backend performance data; provides recommendations to improve performance.
• Performs wafer level process characterization on thin film recording heads using FIB and CD-SEM to identify defects and propose corrective actions.

Skills

Analytical thinking

Experiment design

Root cause analysis

Communication

Education

Bachelor’s degree in Electrical Engineering, Materials Science, or Physics

Master’s or PhD preferred

Tools

JMP

MS Visual Basic

Microsoft Office

Job description

Headway Technologies in Milpitas, California, is seeking an Integration Engineer to advance prototype wafer processes for new technology programs. You will perform wafer-level characterization, analyze backend performance data, and recommend corrective actions to ensure robust processes.

The role requires a PhD or Master’s in a related field (or equivalent experience) and hands-on semiconductor process experience. Proficiency with JMP and Microsoft Office is expected.