Wafer Process Integration Engineer

Headway Technologies; Milpitas (CA); On-site; USD 96,655 - 142,000; Full time

Job summary

Headway Technologies in Milpitas, CA seeks a Process Integration Engineer to advance prototype wafer processes for new technology programs. You will perform wafer-level characterization, conduct failure analyses, and review backend performance data to drive corrective actions.

The role requires hands-on semiconductor process integration experience, proficiency with JMP and MS Office, and strong analytical and communication skills. Office-based with potential facility access and safety adherence.

Qualifications

• Bachelor’s degree in Electrical Engineering, Materials Science, or Physics; Master’s/PhD preferred.
• Two years in process integration or characterization in semiconductor manufacturing or similar.
• Hands-on experience using JMP or similar analytical tools.
• Proficient in Microsoft Office.

Responsibilities

• Develops process integration and characterization techniques for new programs.
• Conducts failure analysis and defines corrective actions.
• Participates in characterization/integration projects within timeframes.
• Performs wafer-level characterization using FIB to identify defects and propose fixes.
• Analyzes inline/backend data and suggests improvements to device performance.
• Designs experiments to verify process robustness and reports results.
• Uses JMP/MS tools to identify root causes of variations and presents findings.
• Responds to inquiries from team members and management.
• Adheres to safety policies and performs related duties.

Skills

Process integration

Data analysis

Root cause analysis

Communication

Time management

Education

Bachelor’s degree in Electrical Engineering, Materials Science, or Physics and/or equivalent relevant experience

Tools

JMP

MS Visual Basic

Microsoft Office

Job description

Headway Technologies in Milpitas, CA seeks a Process Integration Engineer to advance prototype wafer processes for new technology programs. You will perform wafer-level characterization, conduct failure analyses, and review backend performance data to drive corrective actions.

The role requires hands-on semiconductor process integration experience, proficiency with JMP and MS Office, and strong analytical and communication skills. Office-based with potential facility access and safety adherence.