Process Integration Engineer (Semiconductor Yield & HVM)

Construction Job Board USA; Lafayette (OR); On-site; USD 116,000 - 164,000; Full time

Benefits offered by this job

Stock options

Bonuses

Health insurance

Retirement plan

Vacation

Job summary

Intel is seeking a PhD-qualified engineer to lead process-flow development for advanced technology nodes in the US. You will work closely with lithography, etch, deposition, diffusion, and metrology teams to establish robust process windows and integration schemes.

You will perform root-cause analysis, use SPC/DOE/FMEA, and drive corrective actions to optimize yield, CD, overlay, and device performance in collaboration with device and equipment engineers.

Qualifications

• PhD in a relevant hard science or engineering discipline.
• Experience in semiconductor device fabrication, nanotechnology, or related fields.
• Ability to perform statistical analysis and root-cause investigations.

Responsibilities

• Develop and define front end process flows for new technology nodes.
• Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, and metrology teams.
• Establish process windows and integration schemes.
• Drive yield improvement and defect reduction through analysis.
• Tune process conditions with device engineers to meet targets.
• Support ramp from R&D to high-volume manufacturing.

Skills

Statistical process control

Root cause analysis

DOE

FMEA

Cross-functional collaboration

Education

PhD in Electrical Engineering, Physics, Applied Physics, Optics, Materials Science, Chemical Engineering, Mechanical Engineering or related

Tools

JMP

MATLAB

Python

JSL

TCL

SQL

C/C++

Job description

Intel is seeking a PhD-qualified engineer to lead process-flow development for advanced technology nodes in the US. You will work closely with lithography, etch, deposition, diffusion, and metrology teams to establish robust process windows and integration schemes.

You will perform root-cause analysis, use SPC/DOE/FMEA, and drive corrective actions to optimize yield, CD, overlay, and device performance in collaboration with device and equipment engineers.