Lead Physical Design Engineer

Oho Group; San Francisco (CA); On-site; USD 180,000 - 260,000; Full time

Job summary

Oho Group partners with a well-funded AI hardware startup to build an autonomous engineering platform that uses AI agents to optimize custom silicon creation. We seek an Implementation Lead to bridge traditional physical design with AI-assisted layout flows.

You will lead end-to-end backend execution across complex ASICs and ML hardware, defining floorplanning, power/clock architecture, and signoff. Collaborate with ML researchers and hardware architects to push PPA boundaries and integrate

Qualifications

• Proven track record with full-flow tapeouts in ASIC/AI hardware.
• Experience delivering end-to-end physical implementation for complex silicon.
• Strong background in STA, DRC/LVS and power/EM/IR integrity.

Responsibilities

• Lead end-to-end backend execution across complex custom ASICs and ML hardware.
• Direct physical implementation strategy, including floorplanning, power/clock architecture, and physical signoff.
• Build and scale automated physical-design pipelines to improve PPA metrics.
• Integrate agentic AI frameworks and next-gen EDA automation into layout iteration and design closure.
• Collaborate with ML researchers and hardware architects to shape AI-assisted silicon engineering.

Skills

Physical design

Tapeouts

STA

DRC/LVS

Power integrity

Python scripting

Tcl scripting

AI/ML in EDA

RL-based methods in EDA

Tools

Python

Tcl

EDA Automation

Job description

We are partnering with a well-funded AI hardware platform startup collaborating directly with top-tier AI labs.

They are building an autonomous engineering platform that leverages AI agents to optimize custom silicon creation, and they are seeking an Implementation Lead to bridge traditional physical design with AI-assisted layout flows.

What You'll Do:

• Lead end-to-end backend execution across complex custom ASICs and specialized machine learning hardware.
• Direct physical implementation strategy, including floorplanning, power/clock architecture, and physical signoff.
• Build and scale automated physical-design pipelines to continuously push performance, power, and area (PPA) boundaries.
• Integrate agentic AI frameworks and next-generation EDA automation into layout iteration and design closure.
• Collaborate directly with ML researchers and hardware architects to define the future of AI-assisted silicon engineering.

What We're Looking For:

• Proven track record in physical design with multiple successful full-flow tapeouts.
• Deep expertise across physical implementation, static timing analysis (STA), DRC/LVS closure, and power/signal integrity (EM/IR).
• Strong hands-on automation skills in scripting environments (Python/Tcl) alongside experience applying AI/ML or RL-based methods to EDA flows.

Keywords:

RTL to GDS / Physical Design / Floorplanning / STA / DRC / LVS / EM/IR / PPA / EDA Automation / Python / Tcl / Agentic AI / AI Accelerator / Reinforcement Learning / Tapeout