AI-Driven Analog Layout Automation Engineer

Apple

Beaverton (OR)

On-site

USD 140,000 - 210,000

Full time

4 days ago
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Job summary

Apple Inc. is seeking a highly skilled Analog Layout Automation Engineer in Beaverton, OR to help define the next generation of SOCs.

You will convert concepts into silicon, collaborate with circuit designers, and leverage AI-powered CAD tools to create high-performance analog and mixed-signal layouts. The role emphasizes automation, scripting, and data-driven design insights, with emphasis on LVS/DRC/ERC validation, device matching, low noise, and power; experience with Cadence tools and

Qualifications

  • BS degree and at least 10 years of relevant industry experience.
  • Experience designing analog and mixed-signal layouts in advanced CMOS/FinFET tech.
  • Strong programming/scripting in Python, TCL, or Perl; layout automation
  • Experience with AI/ML for layout optimization and data-driven design insights

Responsibilities

  • Convert design concepts into silicon by collaborating with circuit designers and CAD tools.
  • Review floor plans and analyze circuits for high-performance analog/mixed‑signal layouts.
  • Run verification suites and resolve LVS/DRC/ERC issues.
  • Develop scripts to automate layouts and workflows; apply AI/ML for optimization.
  • Collaborate with cross-functional teams to deliver next‑gen SOCs.

Skills

Analog layout
Layout automation
Python
PyTorch
CAD tools
Data analysis
Cross-functional collaboration

Education

BS degree in Electrical Engineering or related field

Tools

Cadence Virtuoso (XL, EAD, APR)
Cadence Innovus
LVS/DRC/ERC tooling

Job description

Apple Inc. is seeking a highly skilled Analog Layout Automation Engineer in Beaverton, OR to help define the next generation of SOCs.

You will convert concepts into silicon, collaborate with circuit designers, and leverage AI-powered CAD tools to create high-performance analog and mixed-signal layouts. The role emphasizes automation, scripting, and data-driven design insights, with emphasis on LVS/DRC/ERC validation, device matching, low noise, and power; experience with Cadence tools and

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