IC Design Engineer (STA/ Synthesis)

Broadcom, Inc.; San Jose (CA); On-site; USD 144,000 - 230,000; Full time

Benefits offered by this job

401(k) matching

Employee Stock Purchase Program (ESPP)

Paid holidays

Paid sick leave and vacation

Job summary

Broadcom, Inc. in San Jose, CA seeks a lead STA/Synthesis engineer to drive timing closure for complex IP and ASIC blocks in advanced nodes.

You will develop timing constraints, run static timing analysis with PrimeTime/Tempus, perform synthesis and timing audits, and automate analysis with Tcl or Perl; provide clock tree guidance.

Requires 12+ years in high‑complexity silicon, RTL/P&R experience, and strong collaboration skills.

Qualifications

• Experience with high-complexity silicon in advanced technology nodes.
• Timing constraint development for hierarchical designs.
• Knowledge of clock tree planning and SoC implementation.
• Experience with timing ECO creation and final signoff.
• Proficiency with STA tools (PrimeTime/TCM/Tempus) and scripting.
• Proficiency with synthesis and audit tools (DC-T/Genus/Fishtail/VCLP/Formality).
• Strong RTL and place-and-route understanding.
• Excellent problem-solving and teamwork skills.

Responsibilities

• Develop and validate timing constraints for intricate SoCs.
• Perform STA using PrimeTime/Tempus and run synthesis with audits.
• Define timing signoff methodologies across corners and derates.
• Conduct pre-route timing checks and QoR analysis.
• Automate timing analysis with Tcl/Perl scripting.
• Guide clock tree synthesis and energy-efficient optimizations.
• Ensure compliance with timing signoff checklists and criteria.
• Generate timing ECOs and drive timing closure for IP/ASIC blocks.

Skills

STA/Timing analysis

Scripting (Tcl, Perl)

Clock tree planning

Timing signoff

Problem-solving

Communication

Teamwork

Independent work

Education

Bachelor's degree in a related field

MS/PhD considered

Tools

PrimeTime

Tempus

TCM

Tempus

DC-T

Genus

Fishtail

VCLP

Formality

Job description

Please Note:1. If you are a first time user, please create your candidate login account before you apply for a job.2. If you already have a Candidate Account, please Sign-In before you apply.Job Description:Broadcom is looking for a lead STA/ Synthesis engineer. In this role, you will be contributing to constraint development, constraint validation, synthesis, audits (CDC, RDC, Static Equivalence, Low Power) and timing closure of mission critical IP and ASIC blocks in advanced technology nodesResponsibilities Include:Develop and validate timing constraints for intricate SoC designs.Perform static timing analysis (STA) using industry-standard tools (e.g., PrimeTime, Tempus)Perform synthesis and run static audits (CDC, RDC, Low Power, equivalence) for high speed, complex digital and mixed signal blocksDefine and implement timing signoff methodologies, including process corners, derates, and uncertainties.Conduct pre-route timing checks and quality of results (QoR) analysis.Automate timing analysis processes using scripting languages such as Tcl or Perl.Provide guidance on clock tree synthesis and optimization for energy-efficient designs.Ensure compliance with timing signoff checklists and criteria.Generate timing ECO's for timing closureDrive timing closure for complex IP and ASIC blocksQualifications:Experience with high-complexity silicon in advanced technology nodes.Familiarity with timing constraint development for hierarchical designs.Knowledge of clock tree planning and implementation for SoCs.Experience with timing ECO creation and final timing signoff.Proficiency in using STA tools (e.g., PrimeTime, TCM, Tempus) and scripting languages (e.g., Tcl, Perl).Proficiency in using synthesis and audit tools (DC-T, Genus, Fishtail, VCLP, Formality)Strong understanding of ASIC design flows, including RTL and place-and-route.Excellent problem-solving skills and attention to detail.Effective communication and teamwork abilities.Ability to work independently in a fast paced, cross geographical environment.Direct or indirect experience with RTL/ Design is a plusAt a minimum Bachelors and 12+ years of related experience or Masters degree and 10+ years of related experience or PhD and 7+ years of related experience. At this level post-graduate coursework is highly desirableCompensation and BenefitsThe annual base salary range for this position is USD 143,800.00 To USD 230,000.00As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.