Hybrid VLSI Physical Design Engineer

Hewlett Packard Enterprise; Fort Collins, Chippewa Falls, BLOOMINGTON (CO, WI, MN); Hybrid; USD 115,000 - 218,000; Full time

Benefits offered by this job

Health & wellbeing

Personal & professional development

Inclusive culture

Job summary

Hewlett Packard Enterprise in Fort Collins, Colorado seeks a VLSI Physical Design Engineer to join our hybrid team. You will perform static timing analysis, drive timing closure, and contribute to synthesis, floorplanning, ECOs, and flow automation for advanced ASIC projects.

The role requires a Bachelor's or Master's in Electrical/Computer Engineering and 1–6 years of VLSI experience. Expect collaboration with architecture, design, and back-end teams in a fast-paced environment.

Qualifications

• Bachelor's or Master's degree in Electrical or Computer Engineering.
• 1–6 years of VLSI design, verification, or implementation.
• Strong knowledge of VLSI fundamentals, digital logic and computer architecture.
• Experience with ASIC flows and EDA tools.

Responsibilities

• Perform static timing analysis for hierarchical designs.
• Create, validate, and maintain timing constraints and budgets.
• Drive timing closure for partition and full-chip designs.
• Analyze timing reports, identify critical paths, and apply fixes.
• Perform synthesis, netlist quality checks, and formal verification.
• Support floorplanning, partitioning, and physical design implementation.
• Create and manage ECOs and flow automation improvements.
• Collaborate with cross-functional teams and mentor others.

Skills

Static timing analysis

Timing closure

Synthesis & netlist QA

Formal verification

Floorplanning & partitioning

ECO implementation

EDA scripting

Programming basics

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Synopsys Fusion Compiler

Design Compiler

PrimeTime

Formality

Cadence Genus

LEC

Job description

Hewlett Packard Enterprise in Fort Collins, Colorado seeks a VLSI Physical Design Engineer to join our hybrid team. You will perform static timing analysis, drive timing closure, and contribute to synthesis, floorplanning, ECOs, and flow automation for advanced ASIC projects.

The role requires a Bachelor's or Master's in Electrical/Computer Engineering and 1–6 years of VLSI experience. Expect collaboration with architecture, design, and back-end teams in a fast-paced environment.