Principal Package Design Engineer

Renesas Electronics; San Jose (CA); Hybrid; USD 200,000 - 240,000; Full time

Benefits offered by this job

Bonus opportunities

Competitive benefits

Job summary

Renesas Electronics in San Jose is seeking a Principal Package Design Engineer to lead next-generation packaging for high-performance semiconductors. You will drive architecture, simulation, and qualification, interfacing with design, manufacturing, and suppliers to ensure robust, scalable solutions.

The role emphasizes hands-on development, collaboration across teams, and leadership in packaging initiatives, with opportunities to influence AI infrastructure and data center power applications.

Qualifications

• MSc or PhD in Electrical Engineering or related field.
• 5+ years in advanced semiconductor packaging or electronics packaging.
• Strong hands-on knowledge of packaging technologies, materials, and integration for AI infrastructure.
• Experience with OSATs, supply chains, and qualification standards.

Responsibilities

• Lead design, development, and qualification of advanced packaging solutions.
• Define architecture with electrical, thermal, mechanical, and cost requirements.
• Collaborate with IC design, substrate, thermal, reliability, and manufacturing teams.
• Develop assembly flows and qualification activities with OSATs.
• Mentor engineers and lead packaging initiatives.

Skills

Advanced packaging concepts

Thermal & mechanical simulations

Cross-functional leadership

DFM/DFX knowledge

Education

MSc or PhD in Electrical Engineering

Tools

Cadence Allegro

SolidWorks

ANSYS

COMSOL

JMP / Minitab

Job description

At Renesas, we are more than just a semiconductor company; we are the engine behind a \"safer, smarter, and more sustainable\" future. Headquartered locally in the heart of San Jose, our Silicon Valley team is at the forefront of innovation in Automotive, Industrial, Infrastructure, and IoT technologies. By blending cutting-edge embedded processing with world-class analog and power expertise, we develop \"Winning Combinations\" that power billions of intelligent devices globally. Joining our San Jose office means joining a collaborative, forward-thinking environment where your work directly impacts the next generation of AI-driven infrastructure and green energy solutions.

Job Description

Principal Package Design Engineer

Location: Hybrid at main Renesas Electronics America locations (San Jose, CA / Austin, TX)

Department: Semiconductor Power Product Group

Reports To: Senior Principal, Device Design Packaging Technology, Strategy, Operations

Position Summary

We are seeking a Principal Package Design Engineer to lead the development and integration of next-generation packaging solutions for high-performance semiconductors and electronic products. This role will focus on advanced package architecture, assembly processes, thermal and mechanical reliability, and cross-functional collaboration with design, applications, product engineering, manufacturing, suppliers, and quality teams. The ideal candidate has deep expertise in semiconductor packaging technologies and a strong track record of bringing complex products from concept through qualification and high-volume production.

Key Responsibilities

• Lead Advanced Packaging Initiatives: Lead the design, development, and qualification of advanced semiconductor packaging solutions, including:
  • Flip-chip, Chip Embedding
  • Wafer-level packaging (WLP/FOWLP)
  • Panel-level packaging (laminate, molding)
  • 2.5D/3D packaging
  • System-in-package (SiP)
  • Ball grid array (BGA/CSP)
  • Wafer-to-wafer and die-to-wafer heterogeneous bonding
• Architecture & Simulation: Define package architecture based on electrical, thermal, mechanical, reliability, and cost requirements with hands-on, deep simulation expertise.
• OSAT & Vendor Strategy: Drive package technology and OSAT selection and development for new product introductions (NPI).
• Cross-Functional Collaboration: Work closely with IC design, product definers, substrate, board, thermal, reliability, applications, and manufacturing teams to ensure package compatibility and performance.
• Layout & Stack-Up: Oversee package layout reviews, stack-up definition, material selection, and interconnect strategy.
• Simulations & Modeling: Perform and guide others on simulations and analysis related to:
  • Signal integrity / power integrity
  • Thermal performance
  • Mechanical stress / warpage
  • Design for manufacturability (DFM)
• Assembly & Qualification: Develop assembly flows and process requirements for OSATs and manufacturing partners. Lead package qualification activities, including DOE planning, failure analysis, and reliability testing.
• Yield & Issue Resolution: Resolve packaging-related issues and challenges during NPI prototype builds, qualification, and production ramp. Collaborate with suppliers and internal/external manufacturing partners on process improvements, material evaluation, and yield optimization.
• Documentation & Leadership: Create and maintain package specifications, design rules, process documentation, and technical reports. Mentor junior engineers and provide technical leadership across packaging initiatives.

Qualifications

Required Qualifications

• Education: MSc or PhD degree in Electrical Engineering, Materials Science, Mechanical Engineering, Chemical Engineering, or a related field.
• Experience: 5+ years of experience in advanced semiconductor packaging or advanced electronics packaging and system integration.
• Technical Depth: Strong hands‑on knowledge of advanced packaging technologies, materials, assembly processes, and application system integration as they apply to AI infrastructure and data center power management.
• Reliability & Tools: Deep understanding of thermal, mechanical, and electrical interactions in package design and extensive, hands‑on model setup, simulations, and analysis. Strong background in CAD and simulation tools. Experience with package reliability testing and qualification standards.
• Supply Chain: Experience working with OSATs, substrate vendors, assembly houses, and semiconductor supply chains.
• Problem Solving & Leadership: Proven ability to troubleshoot packaging failures, drive root cause/corrective action, and demonstrate strong project leadership and cross‑functional communication skills.

Preferred Qualifications

• Master’s or PhD in a relevant engineering discipline.
• Experience with power semiconductor devices and packaging including Si/SiC/GaN MOSFETs, Power Modules, Intelligent Power Modules, and their applications in consumer, industrial, automotive, and high‑performance computing markets.
• Experience with power products in high‑performance computing, AI/ML hardware, or mobile products.
• Hands‑on experience with tools for package design and simulation such as:
  • Cadence Allegro Package Designer
  • SolidWorks
  • ANSYS
  • COMSOL
  • JMP / Minitab
• Knowledge of JEDEC standards, IPC standards, and semiconductor qualification methods.
• Experience in W2W, D2W, D2D 3D heterogeneous integration and chiplet-based packaging.

Key Skills

• Advanced package concept engineering and design
• Materials selection and development
• Thermal and mechanical simulations and analysis
• Failure analysis & reliability engineering
• Design for Manufacturability (DFM/DFX)
• Process development & supplier collaboration
• Technical leadership & problem‑solving

Success in This Role

• Deliver robust package solutions that meet performance, reliability, and cost targets.
• Enable smooth product transfer from concept to development to manufacturing.
• Reduce packaging risks through strong technical analysis, hands‑on simulations, and qualification planning.
• Improve yield, quality, and manufacturability through collaboration with internal and external partners.

Working Conditions

• May require occasional travel to supplier, OSAT, or design/manufacturing/R&D sites.

Additional Information

The expected annual pay range for this position is $200,000-$240,000. This position is also eligible for bonus opportunities. Please note that the final offer amount will be dependent on geographic location, applicable experience, and skillset of the candidate.

Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world-leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.

At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.

We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.

Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Renesas Electronics deals with dual‑use technology that is subject to U.S. export controls regulations. Under these regulations it may be necessary for Renesas to obtain U.S. government export license prior to release of technology to certain persons. The decision whether or not to file or pursue an export license application is at the sole discretion of Renesas.