Hybrid Lead DV Manager - Mixed-Signal/SystemVerilog

Sierra Wireless; San Jose (CA); Hybrid; USD 116,000 - 216,000; Full time

Job summary

Semtech Corporation in San Diego, CA or San Jose, CA, is seeking a Design Verification Manager for a hybrid role. You will lead a distributed verification team across projects and drive comprehensive verification strategies for digital and mixed-signal IC designs.

You will mentor engineers, develop test plans, and manage RTL/AMS verification environments while coordinating with system, firmware, and analog teams to ensure high-quality silicon validation and production readiness.

Qualifications

• 10+ years of industry experience in integrated circuit design verification (DV).
• Experience leading, mentoring or informally managing engineers or projects.
• Strong analytical, synthesis and problem-solving skills.
• In-depth knowledge and experience in digital integrated circuit verification with MCU-based hardware systems (ARM, RISC-V, PIC, STM32) with memories, custom digital micro-architecture, interfaces, dedicated hardware peripherals, external IPs, and analog peripherals.

Responsibilities

• Lead, mentor and develop a team of geographically distributed verification engineers across multiple projects.
• Drive definition and implementation of comprehensive verification strategies, test plans for digital/mixed-signal designs at block and top levels.
• Manage testbenches using SystemVerilog and UVM; lead RTL, gate-level and AMS verification; develop directed tests and coverage models.
• Report progress with metrics and coverage analysis; mitigate verification risks early.
• Interface with system, digital hardware, embedded firmware, analog, and cross-functional teams.
• Drive adoption of advanced verification methodologies and tool evaluation.
• Provide technical support to silicon lab evaluation, test, product and application engineers.

Skills

Team leadership

SystemVerilog

UVM

RTL verification

Debugging

Python

Scripting

Communication

Education

B.S. or M.S. in Electrical or Computer Engineering

Tools

SystemVerilog

UVM

Verilog/VHDL

Python

Cadence

Synopsys

Job description

Semtech Corporation in San Diego, CA or San Jose, CA, is seeking a Design Verification Manager for a hybrid role. You will lead a distributed verification team across projects and drive comprehensive verification strategies for digital and mixed-signal IC designs.

You will mentor engineers, develop test plans, and manage RTL/AMS verification environments while coordinating with system, firmware, and analog teams to ensure high-quality silicon validation and production readiness.