Senior Design Verification Manager – Mixed-Signal ICs

Semtech; San Diego (CA); Hybrid; USD 116,000 - 216,000; Full time

Job summary

Semtech is seeking a Design Verification Manager for the Sensing Product Group in the San Diego area. You will lead a geographically distributed verification team and drive full verification strategies for digital and mixed-signal IC designs.

The role requires 10+ years in DV, strong SystemVerilog/UVM expertise, and the ability to collaborate with system, firmware, analog, and cross-functional teams. Hybrid work model with a focus on scalable verification processes.

Qualifications

• 10+ years of industry experience in integrated circuit design verification (DV).
• B.S./M.S. in Electrical or Computer Engineering or equivalent.
• Experience leading, mentoring or informally managing engineers or projects.
• Strong analytical, synthesis and problem-solving skills.
• In-depth knowledge of digital IC verification with MCU-based hardware systems (ARM, RISC-V, PIC, STM32).
• Proficiency in SystemVerilog as high-level verification language and UVM; Verilog/VHDL; scripting languages (Python, Perl); and EDA tools.

Responsibilities

• Lead, mentor and develop a team of verification engineers across multiple projects.
• Drive definition and implementation of verification strategies and test plans for digital/mixed-signal designs.
• Develop testbenches using SystemVerilog/UVM; manage RTL, gate-level, and AMS verification.
• Report progress with metrics and coverage analysis; mitigate risks early.
• Interface with system, digital hardware, embedded firmware, analog, and cross-functional teams.

Skills

Leadership

SystemVerilog/UVM

Digital verification

Scripting (Python, Perl)

Communication skills

Education

B.S./M.S. in Electrical or Computer Engineering

Tools

Verilog/VHDL

EDA tools (Synopsys, Cadence, Siemens)

MCU familiarity (ARM, RISC-V)

Job description

Semtech is seeking a Design Verification Manager for the Sensing Product Group in the San Diego area. You will lead a geographically distributed verification team and drive full verification strategies for digital and mixed-signal IC designs.

The role requires 10+ years in DV, strong SystemVerilog/UVM expertise, and the ability to collaborate with system, firmware, analog, and cross-functional teams. Hybrid work model with a focus on scalable verification processes.