Hybrid GPU Logic Design Engineer

Intel Corporation; Folsom (CA); Hybrid; USD 142,000 - 200,000; Full time

Job summary

Intel Corporation in California, US, is seeking a GPU Logic Design Engineer to shape graphics IPs and drive RTL design and verification across GPU blocks. The role emphasizes architecture work, microarchitecture features, and collaboration with SoC customers to ensure high-quality integration.

You will optimize designs for power, performance, area, timing, and physical implementation, perform validation, and produce technical documentation.

Qualifications

• Bachelors/Masters/PhD in Electrical/Computer Engineering or related field.
• Experience translating architecture specs into low-level RTL.
• Knowledge of GPU architecture fundamentals and hardware design concepts.

Responsibilities

• Develop logic designs and RTL coding for graphics IPs.
• Define architecture and microarchitecture features for GPU blocks.
• Optimize logic design for power, performance, area, timing, and physical implementation goals.
• Conduct and review unit-level verification to ensure design integrity.
• Debug failing RTL tests and implement corrective measures.
• Collaborate with SoC customers to ensure high-quality GPU block integration.
• Perform power and performance analysis and optimization to meet project goals.
• Deliver technical documentation to promote effective communication and knowledge sharing.
• Manage floating point conversions (float↔fix) as part of GPU logic.
• Demonstrate GPU validation, debugging, and bringing logic designs into high-volume production.

Skills

RTL design

SystemVerilog coding

Architecture specs

GPU architecture knowledge

Education

Bachelor's degree in Electrical or Computer Engineering

Master's degree in Electrical or Computer Engineering

PhD in related field

Tools

Static timing analysis tools

Job description

Intel Corporation in California, US, is seeking a GPU Logic Design Engineer to shape graphics IPs and drive RTL design and verification across GPU blocks. The role emphasizes architecture work, microarchitecture features, and collaboration with SoC customers to ensure high-quality integration.

You will optimize designs for power, performance, area, timing, and physical implementation, perform validation, and produce technical documentation.