Hybrid DFT Application Engineer — ASIC/SoC Validation

Intel Corporation; United States; Hybrid; USD 122,000 - 232,000; Full time

Job summary

Intel Foundry Services seeks a DFT Application Engineer to provide technical support to customers on DFT/DFM insertion, ATPG validation, and PDK usage, focusing on aerospace, defense, and government tape-outs with high quality standards.

You will collaborate with RTL/Hard IP teams and physical designers, develop training materials, and drive best practices for DFT implementations across block and SOC levels.

Qualifications

• US Citizenship required and ability to obtain US Government Security Clearance.
• Bachelor’s degree in Electrical/Computer Engineering or STEM field.
• 3+ years of experience with advanced CMOS processes (22nm and below).
• 3+ years implementing ASIC DFT/DFM insertion (MBIST, LBIST, SCAN, JTAG) at ASIC block and full-chip levels, including ATPG validation and DFT timing/signoff at SOC level.
• 2+ years of scripting with Python, Perl, Tcl, or shell scripting.

Responsibilities

• Provide comprehensive DFT tool/flow/methodology support to address customer issues and ensure successful tape-outs.
• Collaborate with RTL/Hard IP designers on DFT/DFM implementation and work with physical designers on timing signoff.
• Develop and optimize DFT insertion flows for advanced CMOS processes and multi-die designs.
• Develop application notes, documentation, and deliver training to customers and internal teams.

Skills

DFT/DFM insertion

ATPG validation

Python/Perl/Tcl scripting

Customer-facing

Education

Bachelor’s degree in Electrical/Computer Engineering or STEM

Tools

EDA tools for MBIST/SCAN/JTAG

PDK tooling

Job description

Intel Foundry Services seeks a DFT Application Engineer to provide technical support to customers on DFT/DFM insertion, ATPG validation, and PDK usage, focusing on aerospace, defense, and government tape-outs with high quality standards.

You will collaborate with RTL/Hard IP teams and physical designers, develop training materials, and drive best practices for DFT implementations across block and SOC levels.