DFT Application Engineer

Intel Corporation; Chandler (AZ); On-site; USD 90,000 - 130,000; Full time

Benefits offered by this job

Competitive compensation

Stock bonuses

Professional development opportunities

Job summary

Intel Corporation is looking for a DFT Application Engineer in Chandler, Arizona, to provide technical support for foundry services. This includes DFT/DFM insertion and ATPG validation methodologies for aerospace, defense, and government customers.

The ideal candidate will have at least 3 years of experience in ASIC design, a strong customer focus, and proficiency in using EDA tools. The position offers competitive compensation and opportunities for professional development.

Qualifications

• U.S. citizenship required and ability to obtain U.S. Government Security Clearance.
• 3+ years of experience with advanced CMOS processes (22nm and below).
• Proficiency with major EDA tools for DFT validation.

Responsibilities

• Provide comprehensive DFT tool/flow/methodology support.
• Drive quality improvements in ASIC DFT/DFM.
• Deliver customer-facing technical support and guidance.

Skills

Customer Focused

Self-Motivated

Collaborative

Analytical

Communication

Education

Bachelor’s degree in Electrical Engineering, Computer Engineering, or STEM-related field

Post-graduate degree in Electrical/Computer Engineering or STEM-related field

Tools

EDA tools for MBIST insertion

Python

Perl

Tcl

Job description

Position Overview

We seek a DFT Application Engineer to provide technical support to Intel Foundry Services customers on PDKs, DFT/DFM insertion, and ATPG validation methodologies. This role supports Aerospace, Defense, and Government customers in achieving successful tape-outs while ensuring the highest quality standards through comprehensive DFT solutions and customer engagement.

Key Responsibilities

• Provide comprehensive DFT tool/flow/methodology support to address customer issues and challenges, ensuring successful tape-outs and maximum customer satisfaction.
• Work closely with internal Intel teams and external stakeholders, including foundry customers’ design teams, IP providers, and EDA vendors, to resolve complex technical issues.
• Deliver customer‑facing technical support and guidance on DFT implementation strategies.
• Drive quality improvements in ASIC DFT/DFM and ATPG validation methodology, capability/flow, and documentation for both block‑level and SoC‑level implementations.
• Collaborate with RTL and hard‑IP designers on DFT/DFM implementation methodology and work with physical designers on DFT/DFM physical implementation, validation, and timing signoff.
• Develop and optimize DFT insertion flows for advanced CMOS processes and multi‑die designs.
• Develop application notes, documentation, and deliver technical training presentations to customers and internal teams.
• Create best practice guidelines and methodology documentation for DFT implementation across various design complexities.
• Support knowledge transfer and capability building for both internal teams and customer organizations.

Essential Skills & Attributes

• Customer‑Focused: Strong customer‑oriented attitude and mindset with commitment to customer success.
• Self‑Motivated: Self‑driven and results‑oriented with ability to manage multiple complex tasks effectively.
• Collaborative: Excellent teamwork skills to drive innovative solutions for customer design implementation challenges.
• Analytical: Strong analytical problem‑solving capabilities for complex DFT challenges.
• Communication: Effective communication skills with experience in collaboration, active listening, and providing constructive technical feedback.

Qualifications

• U.S. citizenship required and ability to obtain U.S. Government Security Clearance.
• Bachelor’s degree in Electrical Engineering, Computer Engineering, or STEM‑related field.
• 3+ years of experience with advanced CMOS processes (22nm and below).
• 3+ years of combined experience in implementing ASIC DFT/DFM insertion (MBIST, LBIST, SCAN, JTAG) at both ASIC design block level and full chip level, including ATPG validation and DFT timing/signoff at SOC level.
• 2+ years of experience in one or more scripting languages (Python, Perl, Tcl, and/or shell scripting).
• Preferred: Active U.S. Government Security Clearance with a minimum of Secret Level.
• Post‑graduate degree in Electrical/Computer Engineering or STEM‑related field.
• Hands‑on experience in Design Implementation and methodology (ASIC design, full‑chip integration, design signoff, LVS, DRC, DFX/DFM, reliability).
• Proficiency with major EDA tools for MBIST insertion, hierarchical SCAN and JTAG insertion, DFT constraint generation and ATPG validation for single‑die and multi‑die designs.
• Experience building/developing quality DFT/DFX insertion flow and ATPG validation flow.
• Experience providing technical direction to engineering teams and customer support.
• Customer‑facing experience in technical roles.
• Experience with state‑of‑the‑art process technology (7nm and below) and PDK‑based technology evaluation.

Benefits

Opportunity to work with cutting‑edge DFT technologies for aerospace, defense, and government applications; direct customer engagement and technical leadership; access to Intel’s advanced foundry technologies and EDA tool suites; competitive compensation and stock bonuses; professional development in DFT methodologies and foundry services; direct impact on national security through advanced semiconductor technology solutions.

Equal Employment Opportunity

All qualified applicants will receive consideration for employment without regard to race, color, religion, sexual orientation, gender identity, or any other characteristic protected by law.