HW/SW Codesign Engineer

Phinity Labs, Inc.; San Francisco (CA); On-site; USD 170,000 - 210,000; Full time

Benefits offered by this job

Health insurance

Retirement plans

Unlimited PTO

Paid parental leave

Lunch and dinner provided in-office

Job summary

Phinity Labs, Inc. in San Francisco invites applications for a HW/SW Codesign Engineer who operates at the silicon–software boundary to define how a new chip will be used, heavily using AI to speed development.

You will design the hardware/software interface, and own firmware, drivers, and runtimes for bring-up. You will balance hardware and software responsibilities, validate across emulation, FPGA, and bring-up, and communicate clearly in a fast-moving environment.

Qualifications

• 6+ years building across the HW/SW boundary: firmware, drivers, runtimes, or embedded systems, with a working understanding of the underlying silicon
• Knowledge of how accelerators and SoCs are programmed: command and queue models, DMA and memory movement, scheduling, and instruction or ISA interfaces
• Experience using AI to develop hardware or software
• Strong communication skills and willingness to try new methods in ambiguous and fast-moving environments

Responsibilities

• Design the hardware/software interface for edge compute chips: the programming model, command processors, memory movement, and runtime-visible scheduling that let software drive the hardware
• Build and own the firmware, drivers, and runtime for chip bring-up and expose its capabilities to software
• Make co-design tradeoffs across the boundary, deciding what belongs in hardware, firmware, or software, and own the technical bar for how they fit together
• Validate the subsystem across emulation, FPGA, and bring-up, making sure software-visible behavior matches intent

Skills

Firmware development

Device drivers

Embedded systems

Hardware/software co-design

AI for hardware

Tools

FPGA

Emulation tools

ASIC verification

Job description

About Phinity

Phinity is building prompt-to-silicon: the agent infrastructure that enables AI agents to design, verify, optimize, and ultimately tape out chips. By 2028, any company will be able to specify a set of requirements for a chip and Phinity will deliver them a GDS file in weeks, not years.

Today, chip development requires large teams, fragmented tools, and multi-year development cycles. We are building a closed-loop system in which models can reason about hardware, use engineering tools, learn from verification feedback, and perform increasingly consequential parts of the chip-development process.

We work with leading frontier AI labs and are building a small team with deep experience across AI research, silicon architecture, design, and verification. Our long-term goal is autonomous tapeout, making custom silicon accessible enough to accelerate technological progress at breakneck speed.

The Role

The HW/SW Codesign Engineer role is for an engineer who works at the boundary between silicon and software and wants to define how a new chip actually gets used, heavily using AI to speed up development. Some example responsibilities include:

• Design the hardware/software interface for edge compute chips: the programming model, command processors, memory movement, and runtime-visible scheduling that let software drive the hardware

• Build and own the firmware, drivers, and runtime for chip bring-up and expose its capabilities to software

• Make co-design tradeoffs across the boundary, deciding what belongs in hardware, firmware, or software, and own the technical bar for how they fit together

• Validate the subsystem across emulation, FPGA, and bring-up, making sure software-visible behavior matches intent

Requirements

1. 6+ years building across the HW/SW boundary: firmware, drivers, runtimes, or embedded systems, with a working understanding of the underlying silicon

2. Knowledge of how accelerators and SoCs are programmed: command and queue models, DMA and memory movement, scheduling, and instruction or ISA interfaces

3. Experience using AI to develop hardware or software

4. Strong communication skills and willingness to try new methods in ambiguous and fast-moving environments

Why you should work with us

Build a real chip with unlimited AI usage

Access non-publicly released foundation models and learn what the frontier of intelligence is before everyone else

Own the hardware/software interface for a novel chip end-to-end

We offer competitive salary and equity. We work in-person from SF and also have benefits including:

• Health insurance

• Retirement plans

• Unlimited PTO

• Paid parental leave

• Lunch and dinner provided in-office