Chip Architect

Phinity Labs, Inc.; San Francisco (CA); On-site; USD 140,000 - 190,000; Full time

Benefits offered by this job

Health insurance

Retirement plans

Unlimited PTO

Paid parental leave

Lunch and dinner provided in-office

Job summary

Phinity Labs, Inc. in San Francisco is seeking an experienced Chip Architect to lead the design of edge compute chips, guiding microarchitecture, PPA, timing, area, and power while balancing physical feasibility.

You will work directly with founders and frontier researchers, making architecture decisions that endure verification and signoff, and evangelizing AI-enabled tooling to accelerate hardware development.

Qualifications

• 8+ years architecting and shipping complex chips or subsystems through tapeout.
• RTL, microarchitecture, PPA optimization, verification, and signoff.
• Experience using AI to develop chips.
• Strong communication in fast-moving environments.

Responsibilities

• Architect and drive development of edge compute chips, owning microarchitecture, PPA, timing, area, power, and physical feasibility.
• Make architecture decisions that survive verification constraints and own the design bar.
• Establish verification and signoff practice across simulation, formal, and physical design.
• Explain design decisions clearly and help encode judgments into tooling for rapid hardware development.
• Collaborate with founders and frontier lab researchers on-chip construction.

Skills

Chip architecture

Edge compute chips

AI-assisted design

Communication skills

Job description

About Phinity

Phinity is building prompt-to-silicon: the agent infrastructure that enables AI agents to design, verify, optimize, and ultimately tape out chips. By 2028, any company will be able to specify a set of requirements for a chip and Phinity will deliver them a GDS file in weeks, not years.

Today, chip development requires large teams, fragmented tools, and multi-year development cycles. We are building a closed-loop system in which models can reason about hardware, use engineering tools, learn from verification feedback, and perform increasingly consequential parts of the chip-development process.

We work with leading frontier AI labs and are building a small team with deep experience across AI research, silicon architecture, design, and verification. Our long-term goal is autonomous tapeout, making custom silicon accessible enough to accelerate technological progress at breakneck speed.

The Role

The Chip Architect role is for an experienced silicon engineer who wants to architect and lead a a chip, heavily using AI to speed up development. Some example responsibilities include:

• Architect and drive the development of edge compute chips, owning the microarchitecture and the PPA, timing, area, power, and physical-feasibility tradeoffs that define a good design
• Make the chip- and subsystem-level architecture decisions that have to survive verification, timing, area, power, and physical constraints, and own the technical bar across the design
• Establish rigorous verification and signoff practice across simulation, formal, and physical design
• Articulate why a design decision is good, and help us encode that judgment into the tooling that lets a small team design hardware at unusual speed
• Work hands-on with unreleased frontier models as part of how the chip gets built

The role will involve you working directly with the founders and collaborating frequently with frontier lab researchers.

Requirements

1. 8+ years architecting and shipping complex chips or subsystems, with designs taken through tapeout
2. Knowledge across the design stack: RTL and microarchitecture, PPA optimization, verification, understanding of physical design and signoff
3. Experience using AI to develop chips
4. Strong communication skills and willingness to try new methods in ambiguous and fast-moving environments

Why you should work with us

• Build a real chip with unlimited AI usage
• Access non-publicly released foundation models and learn what the frontier of intelligence is before everyone else
• Own architecture decisions for novel chip design end-to-end

We offer competitive salary and equity. We work in-person from SF and also have benefits including:

• Health insurance
• Retirement plans
• Unlimited PTO
• Paid parental leave
• Lunch and dinner provided in-office