Head of Wearable SoC Analog Design

Ixana; West Lafayette (IN); On-site; USD 175,000 - 225,000; Full time

Benefits offered by this job

Equity

Relocation support

Visa sponsorship

Comprehensive health insurance

401(k) plan

Paid time off

Job summary

Ixana is seeking an experienced IC design leader to architect next‑generation Wi‑R SoCs and guide mixed-signal teams across West Lafayette and remote sites. You will own end‑to‑end tape-outs, IP reuse strategies, and silicon validation, collaborating with product and firmware to optimize system performance.

The ideal candidate has 15+ years in ASIC/SoC design with multiple tape-outs and deep low‑power wireless experience, plus Cadence proficiency and leadership skills.

Qualifications

• 15+ years in ASIC/SoC design with multiple tape-outs.
• Proven leadership from spec to production.
• Deep experience in low-power wireless SoCs (Bluetooth, NFC, UWB or PHYs).

Responsibilities

• Architect next-generation Wi-R SoCs, integrating analog/RF front-end, ultra-low-power digital blocks, and sensor interfaces.
• Build and lead the IC design team digital, analog, mixed-signal across West Lafayette and remote sites.
• Own chip tape-outs end to end: RTL-to-GDS, IP integration, ESD, packaging co-design, and silicon validation.
• Define and enforce methodologies for IP reuse, verification, and simulation.
• Partner with product, firmware, and hardware teams to co-optimize system design.
• Be the technical face of silicon for investors, partners, and customers.

Skills

SoC design leadership

Tape-out leadership

Low-power wireless experience

Cadence toolchains

Tools

Cadence toolchains

Floorplanning

DFT

Timing closure

Analog/digital integration

Job description

Ixana is seeking an experienced IC design leader to architect next‑generation Wi‑R SoCs and guide mixed-signal teams across West Lafayette and remote sites. You will own end‑to‑end tape-outs, IP reuse strategies, and silicon validation, collaborating with product and firmware to optimize system performance.

The ideal candidate has 15+ years in ASIC/SoC design with multiple tape-outs and deep low‑power wireless experience, plus Cadence proficiency and leadership skills.