Director of Analog Design - Wearable SoCs

Ixana; West Lafayette (IN); On-site; USD 175,000 - 225,000; Full time

Benefits offered by this job

Equity

Relocation support

Visa sponsorship

Comprehensive health insurance

401(k) plan

Paid time off

Job summary

Ixana is seeking an experienced IC design leader to architect next‑generation Wi‑R SoCs and guide mixed-signal teams across West Lafayette and remote sites. You will own end‑to‑end tape-outs, IP reuse strategies, and silicon validation, collaborating with product and firmware to optimize system performance.

The ideal candidate has 15+ years in ASIC/SoC design with multiple tape-outs and deep low‑power wireless experience, plus Cadence proficiency and leadership skills.

Qualifications

• 15+ years in ASIC/SoC design with multiple tape-outs.
• Proven leadership from spec to production.
• Deep experience in low-power wireless SoCs (Bluetooth, NFC, UWB or PHYs).

Responsibilities

• Architect next-generation Wi-R SoCs, integrating analog/RF front-end, ultra-low-power digital blocks, and sensor interfaces.
• Build and lead the IC design team digital, analog, mixed-signal across West Lafayette and remote sites.
• Own chip tape-outs end to end: RTL-to-GDS, IP integration, ESD, packaging co-design, and silicon validation.
• Define and enforce methodologies for IP reuse, verification, and simulation.
• Partner with product, firmware, and hardware teams to co-optimize system design.
• Be the technical face of silicon for investors, partners, and customers.

Skills

SoC design leadership

Tape-out leadership

Low-power wireless experience

Cadence toolchains

Tools

Cadence toolchains

Floorplanning

DFT

Timing closure

Analog/digital integration

Job description

What You’ll Do

• Architect next-generation Wi-R SoCs, integrating analog/RF front-end, ultra-low-power digital blocks, and sensor interfaces
• Build and lead the IC design team digital, analog, mixed-signal across West Lafayette and remote sites
• Own chip tape-outs end to end: RTL-to-GDS, IP integration, ESD, packaging co-design, and silicon validation
• Define and enforce methodologies for IP reuse, verification, and simulation
• Partner with product, firmware, and hardware teams to co-optimize system design
• Be the technical face of silicon for investors, partners, and customers

What we are looking for

Required:

• 15+ years experience in ASIC or SoC design, with at least 3 successful tape-outs in mixed-signal or RF-heavy products
• Proven success leading teams through spec → tape-out → bring-up → production
• Deep experience in low-power wireless SoCs, including Bluetooth, NFC, UWB, or proprietary PHYs
• Proficiency in Cadence toolchains, floorplanning, DFT, timing closure, and analog/digital integration

Preferred:

• Prior work in wearable, bioelectronics, or medical devices

Compensation & Benefits

• Base salary $175 000 - $225 000 USD - equivalent to $330k - $430k Bay-Area purchasing power. 3br houses in Lafayette, IN area are $350k-450K. Top 20 school district in the country.
• 10-50% cash bonus
• Meaningful early-stage equity
• Relocation bonus, partner job- search help All figures based on BestPlaces July 2025 cost-of-living indices. West Lafayette index = 83.5. These reflect real-world purchasing power, not just cash numbers.
• Comprehensive health, dental, and vision insurance
• 401 k retirement plan
• 5 days a week in office. Flexible work arrangements and generous PTO
• Professional development opportunities and conference attendance
• Patent development and technology leadership opportunities
• Immigration and work visa support as long as you are already in US on a work permit
• Full visa sponsorship STEM-OPT transfer / H-1B / TN / future green card

Why Join Us

• Work on deep tech that matters
• Collaborate with world-class experts and industry leaders
• Own your work end-to-end and see real impact
• Enjoy a culture of speed, rigor, and respect
• Competitive perks, equity, and global exposure

Keywords:

Analog IC Design, Mixed-Signal SoC, ASIC Development, Low-Power Wireless Systems, RF Front-End Design, SoC Architecture, Tape-Out & Silicon Validation, Cadence EDA Tools, Wearable Electronics, Root Cause Analysis