HBM Verification Engineer: Architect High-Throughput UVM

Intelliswift - An LTTS Company; San Francisco (CA); On-site; USD 140,000 - 190,000; Full time

Job summary

L&T Technology Services (LTTS) seeks an HBM Verification Engineer to design and implement scalable UVM testbenches for a high-performance memory subsystem. You will develop constrained-random stimuli to stress pseudo-channel concurrency, bank conflicts, and scheduling, driving thorough verification across HBM modes and training cycles.

You will collaborate with RTL designers, performance architects, and compiler teams to emulate transformer attention patterns and locate root causes of

Qualifications

• 3+ years of ASIC verification experience.
• Experience with HBM memory subsystems (HBM2E/HBM3/LPDDR5/DDR5).
• Strong knowledge of JEDEC HBM timing, training loops, and address-hashing schemes.
• Proficiency in SystemVerilog and UVM, with ability to customize VIPs.

Responsibilities

• Design, build, and maintain scalable SystemVerilog/UVM verification environments for the HBM controller and PHY.
• Create constrained-random stimulus to stress throughput, channel concurrency, and scheduling algorithms.
• Define verification plans and drive coverage closure across HBM modes, power states, and training cycles.
• Collaborate with RTL, performance architects, and compiler teams to model transformer attention patterns and root-cause bottlenecks.

Skills

ASIC verification

SystemVerilog/UVM

HBM interfaces

HBM timing knowledge

Emulation experience

Education

Bachelor's in Electrical Engineering

Tools

Palladium emulation

Zebu prototyping

Veloce prototyping

Job description

L&T Technology Services (LTTS) seeks an HBM Verification Engineer to design and implement scalable UVM testbenches for a high-performance memory subsystem. You will develop constrained-random stimuli to stress pseudo-channel concurrency, bank conflicts, and scheduling, driving thorough verification across HBM modes and training cycles.

You will collaborate with RTL designers, performance architects, and compiler teams to emulate transformer attention patterns and locate root causes of