HBM Verification Engineer

Intelliswift - An LTTS Company; San Francisco (CA); On-site; USD 140,000 - 190,000; Full time

Job summary

L&T Technology Services (LTTS) seeks an HBM Verification Engineer to design and implement scalable UVM testbenches for a high-performance memory subsystem. You will develop constrained-random stimuli to stress pseudo-channel concurrency, bank conflicts, and scheduling, driving thorough verification across HBM modes and training cycles.

You will collaborate with RTL designers, performance architects, and compiler teams to emulate transformer attention patterns and locate root causes of

Qualifications

• 3+ years of ASIC verification experience.
• Experience with HBM memory subsystems (HBM2E/HBM3/LPDDR5/DDR5).
• Strong knowledge of JEDEC HBM timing, training loops, and address-hashing schemes.
• Proficiency in SystemVerilog and UVM, with ability to customize VIPs.

Responsibilities

• Design, build, and maintain scalable SystemVerilog/UVM verification environments for the HBM controller and PHY.
• Create constrained-random stimulus to stress throughput, channel concurrency, and scheduling algorithms.
• Define verification plans and drive coverage closure across HBM modes, power states, and training cycles.
• Collaborate with RTL, performance architects, and compiler teams to model transformer attention patterns and root-cause bottlenecks.

Skills

ASIC verification

SystemVerilog/UVM

HBM interfaces

HBM timing knowledge

Emulation experience

Education

Bachelor's in Electrical Engineering

Tools

Palladium emulation

Zebu prototyping

Veloce prototyping

Job description

Fulltime role with L&T Technology Services (LTTS)

The Role

As an HBM Verification Engineer, you will be the ultimate guardian of our memory subsystem's correctness, performance, and reliability. You won't just instantiate generic vendor VIP and run stock tests, you will architect and build robust, high-performance UVM testbenches to stress-test our custom memory controller and physical HBM3E/HBM4 interfaces under extreme transformer-scale workloads (such as massive KV caching and ultra-fast prefill/decode cycles).

What You'll Do

• UVM Testbenches: Design, build, and maintain scalable, protocol-aware SystemVerilog/UVM verification environments from scratch for our custom HBM controller and PHY subsystem.
• Stress Peak Throughput: Create intelligent, highly constrained-random stimulus generators to ruthlessly stress-test pseudo-channel concurrency, bank conflict resolution, and command scheduling algorithms.
• Close Coverage Loops: Define and execute comprehensive verification plans, driving functional and code coverage closure across complex HBM modes, power states, and training cycles.
• Cross-Functional Co-Design: Collaborate directly with RTL designers, performance architects, and our compiler team to emulate real-world transformer attention patterns and root-cause intricate hardware-software bottlenecks.

What We're Looking For

• Silicon Success: 3+ years of ASIC verification experience, with a proven track record of shipping complex, high-speed memory subsystems (HBM2E, HBM3, HBM3E, or LPDDR5/DDR5) to production silicon.
• Deep Protocol Mastery: Intimate, low-level understanding of the JEDEC HBM specification, including timing parameters (tRCD, tRP, tRAS), training loops (WDQS), and complex address-hashing schemes.
• Advanced UVM/SystemVerilog: Expert-level mastery of SystemVerilog and UVM, with the ability to customize verification IPs (VIPs) and write clean, modular checkers and monitors.
• Emulation & Post-Silicon Exposure: Experience with hardware emulation platforms (Palladium, Zebu, Veloce) or FPGA prototyping to accelerate pre-silicon validation and post-silicon bring-up.
• Startup DNA: A bias for action, a high degree of technical autonomy, and a passion for working in fast-moving, high-velocity environments where your work directly impacts product success.