A leading tech firm in Redmond seeks an experienced verification engineer to define and implement UVM environments. Candidates must have over 10 years of experience in UVM testbench development, block level verification, and RTL debugging. The role includes creating test plans and supporting post-silicon verification activities. This position offers an opportunity to work on advanced technology in a dynamic environment.
Qualifications
10+ years of experience in the field is required.
Self-driven individual with extensive debugging experience.
Experience in pre-silicon verification preferred.
Responsibilities
Define and implement a UVM verification environment.
Develop tests and verification collateral.
Debug failures and recommend fixes.
Skills
UVM TB development
block level verification
RTL debugging
Education
BA in electrical or computer engineering
Job description
Skills Required
Years of Experience Required: 10+ overall years of experience in the field.
Degrees or certifications required: BA in electrical or computer engineering (degree is nice to have for this role).
Disqualifiers: Candidates with this will not be eligible for the role: Lack of education or industry mismatching
Best vs. Average: The ideal resume would contain: Self-driven individual; Someone who has worked on pre silicon verification; Extensive debugging experience
Responsibilities
Define, document, and implement a UVM verification environment including agents and scoreboards
Write test plans and implement them by developing tests, test generators, test benches, checkers, coverage, and other verification collateral
Run tests on RTL and Gate Level Netlists, debug failures to root cause, and recommend fixes
Support post-silicon verification activities of the products working with design and product teams
Top 3 Hard Skills Required
10+ years experience with: Expertise in UVM TB development from scratch
10+ years experience with: block level and SOC level verification
10+ years experience with: RTL debugging expertise