IP Design Verification Engineer

Jobtailor; California (MO); On-site; USD 110,000 - 170,000; Full time

Job summary

Jobtailor seeks an experienced verification engineer to lead testbench development and UVM-based verification of complex IP/SoC designs.

Candidates should have strong SystemVerilog/UVM skills, RTL debugging ability, and expertise in constrained-random stimulus, coverage analysis, and SVA assertions. Collaboration with design teams and cross-domain verification will be routine.

Qualifications

• Bachelor's or higher in ECE/CS with 5+ years of experience, or advanced degrees with fewer years.
• IP or SoC verification experience using SystemVerilog/UVM.
• Reading and interpreting technical specs and RTL code for debug.
• Implementation of verification environments including constrained-random stimulus.
• Code/Functional Coverage analysis.
• Writing SystemVerilog Assertions (SVA).

Responsibilities

• Test bench development.
• Directed/constrained random test generation in UVM.
• Collaborate with design team to review specs, define verification plan, coverage, and improve methodology.
• Run RTL and gate-level functional verification, debug failures, and analyze coverage.
• Support mixed-signal verification using Verilog models of analog IP.

Skills

SystemVerilog/UVM

RTL debugging

Constrained-random stimulus

Code/Functional Coverage

Assertions (SVA)

Education

Bachelor's degree in Electrical/Computer Engineering or CS

Master's degree in Electrical/Computer Engineering or CS

PhD in Electrical/Computer Engineering or CS

Tools

Verilog

SystemVerilog

UVM

Job description

Responsibilities

• Test bench development
• Directed/constrained random test generation in UVM
• Closely working with design team to review specifications and architecture, define verification plan, coverage, and improve methodology
• Run RTL and gate level functional verification, debug failures, and analyze coverage
• Support mixed‑signal verification using Verilog models of analog IP

Requirements

• Bachelor's degree in Electrical/Computer Engineering or Computer Science and 5+ years of experience -OR- Master's degree in Electrical/Computer Engineering or Computer Science and 3+ years of experience -OR- PhD in Electrical/Computer Engineering or Computer Science and 2+ years of experience
• IP or SoC verification experience using System Verilog/UVM
• Reading and interpreting technical specs and Register Transfer Level (RTL) code for debug
• Implementation of verification environments that include use of constrained-random stimulus
• Code/Functional Coverage analysis
• Writing System Verilog Assertions (SVA)