GPU PPA Methodology Engineer (RTL to GDS)

MaC VC; San Diego (CA); On-site; USD 170,000 - 254,000; Full time

Job summary

Qualcomm Technologies, Inc. seeks a GPU/ASIC engineer to advance power, performance, and area for state-of-the-art GPU cores. You will work across RTL-to-GDSII, formal verification, and ECO generation, interacting with design, technology, and post-silicon teams.

The role requires strong RTL/SV skills, experience with Synopsys tools, and scripting ability. Collaboration, initiative, and deliverable quality are essential.

Qualifications

• Bachelor's/Master's/PhD in a related field with relevant work experience.
• Experience with RTL to GDSII flows and ASIC design life cycles.
• Strong scripting in UNIX shell, Python, Perl or TCL.

Responsibilities

• Develop and optimize flows/methodologies for PPA improvements.
• Collaborate with design, tech, power, and sign-off teams.
• Drive RTL-to-GDSII delivery and ECO fixes with timing constraints.

Skills

Verilog

SystemVerilog

RTL design

RTL synthesis

PPA optimization

Clock Tree Analysis

ECO methods

Education

Bachelor's degree in Computer Engineering/Computer Science/Electrical Engineering

Master's degree in Computer Engineering/Computer Science/Electrical Engineering

PhD in Computer Engineering/Computer Science/Electrical Engineering

Tools

Synopsys Fusion Compiler

Synopsys RTL-Architect

PrimePower

PrimeTime

Prime Closure

Job description

Qualcomm Technologies, Inc. seeks a GPU/ASIC engineer to advance power, performance, and area for state-of-the-art GPU cores. You will work across RTL-to-GDSII, formal verification, and ECO generation, interacting with design, technology, and post-silicon teams.

The role requires strong RTL/SV skills, experience with Synopsys tools, and scripting ability. Collaboration, initiative, and deliverable quality are essential.