GPU Integration Architect for SoC/RTL & IP Blocks

QUALCOMM, Inc.; San Diego (CA); On-site; USD 204,000 - 306,000; Full time

Job summary

Qualcomm Technologies, Inc. in San Diego is seeking a senior ASIC/GPU design engineer to architect and implement integration IP for high-performance graphics GPUs.

You will perform RTL design and synthesis, logic and timing verification, and integrate complex IP into a complete GPU while coordinating with software, power and design teams. The role requires a strong background in SystemVerilog, multi-clock design, timing concepts, and AMBA protocols, plus Python scripting for automation.

Qualifications

• Bachelor’s degree with 6+ years ASIC design/verification experience.
• Experience with SoC/IP integration and RTL coding in SystemVerilog.
• Strong understanding of timing, clocking, and multi-clock domains.
• Background in AMBA protocols and RTL verification methodologies.

Responsibilities

• Architect and micro-architect integration IP for GPUs.
• RTL design and synthesis for GPU blocks and interfaces.
• Logic and timing verification across multi-discipline teams.
• Integrate complex IP to form a complete GPU system.
• Collaborate with software, power, and design teams to deliver solutions.

Skills

RTL design

SystemVerilog

Synthesis

Timing verification

Multi-clock design

AMBA protocols (AXI/AHB/APB)

Python scripting

Leadership & communication

Education

Bachelor’s degree in Computer/Electrical Engineering or related field

Master’s degree in related field (welcomed)

PhD in related field (welcomed)

Tools

Lint

CDC

Frontend design tools

Synthesis tools

Job description

Qualcomm Technologies, Inc. in San Diego is seeking a senior ASIC/GPU design engineer to architect and implement integration IP for high-performance graphics GPUs.

You will perform RTL design and synthesis, logic and timing verification, and integrate complex IP into a complete GPU while coordinating with software, power and design teams. The role requires a strong background in SystemVerilog, multi-clock design, timing concepts, and AMBA protocols, plus Python scripting for automation.