Senior ASIC Verification Engineer - GPU (Hybrid, Equity)

NVIDIA Corporation; Santa Clara, Northern (CA, KY); Hybrid; USD 136,000 - 265,000; Full time

Job summary

NVIDIA Corporation in Santa Clara, CA is seeking a Senior ASIC Verification Engineer to verify GPUs at the unit level. You will work on testbenches, directed and random tests, and collaborate with RTL and architecture teams to refine microarchitecture and ensure verifiability of design changes.

The role requires 5+ years in ASIC verification, strong SystemVerilog and UVM/SFV experience, good debugging and a collaborative mindset. We offer competitive compensation, equity, and benefits.

Qualifications

• BS or MS in Electrical Engineering or Computer Engineering or equivalent experience.
• 5+ years of ASIC verification experience.
• Strong SystemVerilog, test planning, coverage closure, and test bench design.
• Experience with UVM, SFV, and verification methodologies.

Responsibilities

• Work on a unit-level testbench with directed and random tests and contribute to future testbench methodology.
• Collaborate with RTL and architecture teams to refine microarchitecture plans for verifiability of design changes.
• Architect and plan verification strategy and execution for subsystem features affecting your unit.
• Support post-silicon validation activities and issue debugging with strong problem-solving.
• Exploit AI techniques to accelerate testbench development and automation.

Skills

SystemVerilog

Test planning

Coverage closure

Test bench design

Object oriented programming

Debugging

Teamwork

Education

BS in Electrical Engineering

MS in Electrical/Computer Engineering

Tools

UVM

SFV

SystemVerilog

Verilog

Job description

NVIDIA Corporation in Santa Clara, CA is seeking a Senior ASIC Verification Engineer to verify GPUs at the unit level. You will work on testbenches, directed and random tests, and collaborate with RTL and architecture teams to refine microarchitecture and ensure verifiability of design changes.

The role requires 5+ years in ASIC verification, strong SystemVerilog and UVM/SFV experience, good debugging and a collaborative mindset. We offer competitive compensation, equity, and benefits.