Senior SoC Timing Engineer - STA & Timing Closure Lead

Micron Technology, Inc; Richardson (TX); Hybrid; USD 180,000 - 240,000; Full time

Job summary

Micron Technology, Inc. seeks an experienced SoC Timing (Static Timing Analysis/STA) Engineer (HBM) to own chip-level timing sign-off for next-generation designs.

You will collaborate with RTL, physical design, DFT, verification, and product teams to ensure timing integrity across modes and corners, from design through tape-out. This is a senior, hands-on role focused on constraint authoring, timing closure, methodology development, and pre-/post-silicon timing correlation.

Qualifications

• 10+ years of hands-on experience owning chip-level static timing analysis and full timing sign-off.
• Deep expertise with industry-standard static timing analysis tools such as PrimeTime and/or Tempus.
• Expert understanding of MMMC, OCV, and SI concepts.
• Proven ability to develop and manage complex hierarchical SDC constraints for large SoCs.
• Proficiency in Python and/or Tcl scripting for timing flow automation, constraint management, and quality of results reporting.

Responsibilities

• Own end-to-end chip-level static timing analysis and sign-off across all checks, modes, corners, and voltage/temperature conditions.
• Develop, maintain, and validate SDCs for clocks, resets, HBM interfaces, DFT, and configuration logic.
• Drive timing closure at block, subsystem, and full-chip levels through MMMC analysis and ECOs.
• Collaborate with physical design on placement, clock tree synthesis, and routing to resolve timing issues.
• Lead timing closure efforts with multi-mode, multi-corner considerations and OCIV/POCV analyses.
• Build and maintain STA automation and reporting flows in Python/Tcl for sign-off readiness.
• Mentor engineers and contribute to timing sign-off artifacts and processes.

Skills

Static timing analysis

Chip-level sign-off

Python scripting

Tcl scripting

PrimeTime

Cadence Tempus

Clock-domain crossing

Tools

Synopsys PrimeTime

Cadence Tempus

Job description

Micron Technology, Inc. seeks an experienced SoC Timing (Static Timing Analysis/STA) Engineer (HBM) to own chip-level timing sign-off for next-generation designs.

You will collaborate with RTL, physical design, DFT, verification, and product teams to ensure timing integrity across modes and corners, from design through tape-out. This is a senior, hands-on role focused on constraint authoring, timing closure, methodology development, and pre-/post-silicon timing correlation.