Front-End RTL Design Engineer – High-Speed Datapath

Doist; San Jose (CA); On-site; USD 120,000 - 190,000; Full time

Job summary

Lumilens in San Jose, CA is seeking an IC/RTL Design Engineer to craft front-end RTL, including high-speed datapath interfaces from UCIe to optical front ends. You will implement SystemVerilog blocks, verify with testbenches, and collaborate with DV, DFT, and backend teams for timely silicon bring-up.

The role emphasizes power- and timing-aware design, lint discipline, and hands-on development from micro-architecture through verification handoff, with room to grow as the chip matures.

Qualifications

• BS or MS in Electrical/Computer Engineering (or equivalent).
• 3+ years of digital RTL design in SystemVerilog.
• Strong fundamentals: pipelining, FSMs, FIFOs, CDC/RDC, and streaming/bus interfaces.
• Power- and timing-aware design practices; experience with synthesis and timing closure.

Responsibilities

• Develop block-level micro-architecture for assigned RTL blocks.
• Design and implement front-end RTL in SystemVerilog for datapath elements, UCIe adapter, FIFOs, and related logic.
• Integrate IP and support parameterization for configurability.
• Write clean, lint-clean RTL and block-level testbenches, sanity checks, and SVA for own blocks.
• Assist bring-up across simulation and emulation/FPGA prototyping; support DV and silicon bring-up with DFT hooks.

Skills

SystemVerilog

RTL design

Debug in simulation

Python scripting

Clock-domain crossing

Pipelining

AXI interfaces

Lint/CDc discipline

Education

BS or MS in Electrical/Computer Engineering

Tools

SVA/UVM

Emulation/FPGA prototyping

Job description

Lumilens in San Jose, CA is seeking an IC/RTL Design Engineer to craft front-end RTL, including high-speed datapath interfaces from UCIe to optical front ends. You will implement SystemVerilog blocks, verify with testbenches, and collaborate with DV, DFT, and backend teams for timely silicon bring-up.

The role emphasizes power- and timing-aware design, lint discipline, and hands-on development from micro-architecture through verification handoff, with room to grow as the chip matures.