IC/RTL Design Engineer

Uncover; San Jose, Northern (CA, KY); Hybrid; USD 120,000 - 190,000; Full time

Job summary

Lumilens in San Jose, CA is seeking an IC/RTL Design Engineer to craft front-end RTL, including high-speed datapath interfaces from UCIe to optical front ends. You will implement SystemVerilog blocks, verify with testbenches, and collaborate with DV, DFT, and backend teams for timely silicon bring-up.

The role emphasizes power- and timing-aware design, lint discipline, and hands-on development from micro-architecture through verification handoff, with room to grow as the chip matures.

Qualifications

• BS or MS in Electrical/Computer Engineering (or equivalent).
• 3+ years of digital RTL design in SystemVerilog.
• Strong fundamentals: pipelining, FSMs, FIFOs, CDC/RDC, and streaming/bus interfaces.
• Power- and timing-aware design practices; experience with synthesis and timing closure.

Responsibilities

• Develop block-level micro-architecture for assigned RTL blocks.
• Design and implement front-end RTL in SystemVerilog for datapath elements, UCIe adapter, FIFOs, and related logic.
• Integrate IP and support parameterization for configurability.
• Write clean, lint-clean RTL and block-level testbenches, sanity checks, and SVA for own blocks.
• Assist bring-up across simulation and emulation/FPGA prototyping; support DV and silicon bring-up with DFT hooks.

Skills

SystemVerilog

RTL design

Debug in simulation

Python scripting

Clock-domain crossing

Pipelining

AXI interfaces

Lint/CDc discipline

Education

BS or MS in Electrical/Computer Engineering

Tools

SVA/UVM

Emulation/FPGA prototyping

Job description

# IC/RTL Design EngineerLumilens • San Jose, CA • • 2h agoSave this role or tell us whether you want more jobs like it.**IC/RTL Design Engineer/ Front-End Engineer****About the role.** You design and implement the digital front-end RTL at the heart of the chip — including the high-speed datapath that moves data between UCIe and the optical front end. Guided by the interface specs and coding standards, you take blocks from micro-architecture through clean, timing-aware RTL and block-level verification. It's a hands-on role with room to grow your scope as the team and the chip mature.**What you'll do*** **Develop block-level micro-architecture** for your assigned blocks, and contribute to interface and register definitions.* **Design and implement front-end RTL blocks in SystemVerilog** — datapath elements, the UCIe streaming/RDI adapter, elastic FIFOs, and supporting logic.* **Integrate IP** and support parameterization for configurability.* **Write clean, lint-clean, CDC/RDC-clean RTL** that follows the coding and quality standards.* **Write block-level testbenches, sanity checks, and assertions (SVA)** for your own blocks before handoff to DV.* **Power- and timing-aware design** — managing block activity, clock-gating, pipelining, and retiming; partner with the backend team on physical closure for your blocks.* **Bring-up and debug** across simulation and emulation / FPGA prototyping; support DV and silicon bring-up, including DFT/debug hooks in your blocks.* **Collaborate** with the architecture, modelling, DV, DFT, and backend teams as your blocks move through the flow.**Required*** **BS or MS in Electrical/Computer Engineering** (or equivalent experience).* **3+ years of digital RTL design in SystemVerilog**, with blocks taken from micro-architecture through to verification handoff.* **Solid digital design fundamentals**: pipelining, FSMs, FIFOs, clock-domain crossing, and streaming/bus interfaces (e.g., AXI).* **Lint and CDC/RDC discipline** and clean-RTL practices.* **Power- and timing-aware design practices;** comfort with synthesis and timing closure, working with the backend team.* **Strong debug skills in simulation**; scripting in Python, Perl, or TCL.**Preferred*** **High-speed datapath, SerDes-adjacent, or interface design exposure** (UCIe, PCIe/CXL, or similar).* **FEC/coding datapath familiarity** (e.g., Reed-Solomon) and gray-code mapping.* **Assertion-based verification (SVA)** and familiarity with UVM block-level testbenches; emulation / FPGA prototyping experience.* **Exposure to scale-up / scale-out interconnects** or network switch / NIC / memory-controller datapaths.* **Low-power / UPF and DFT (scan)** concepts**.*** **Optical transceiver, CPO, or linear-drive optics background**; advanced-node (N5/N3/N2) design experience.