Frontend CAD Tools Engineer for SoC Verification

Ericsson GmbH; Austin (TX); Hybrid; USD 120,000 - 180,000; Full time

Job summary

Ericsson Silicon in Austin, Texas is seeking a Front-End CAD Infrastructure and Tools Engineer to shape the verification methodology and tools for SoC designs. You will lead tool flows, drive innovative design processes, and collaborate across design, verification, testing, and manufacturing teams to improve silicon design efficiency.

The role requires hands-on experience with ASIC/SoC design, RTL, Verilog, UVM, and SystemVerilog, plus scripting and regression tooling.

Qualifications

• Experience in ASIC IP/SoC design, RTL, Verilog, UVM, SystemVerilog.
• Exposure to front-end tools including Verilog simulators, RTL/Verification linters, and clock domain crossing checkers.
• Familiarity with synthesis, static timing analysis, and Design-For-Test (DFT).
• Proficiency in scripting languages such as Perl, Python, bash, or csh.
• BS/MS in Electrical Engineering, Computer Science, or similar field; several years of hands-on industry experience.

Responsibilities

• Develop, deploy, and support complex tool flows in Frontend Design & Verification.
• Drive innovation in design processes and methodologies.
• Foster cross-functional collaboration with design, verification, testing, and manufacturing teams.
• Identify and address technical challenges during the silicon design process.
• Implement processes for ensuring silicon design quality through rigorous design reviews and testing methodologies.
• Troubleshoot and optimize workflows to increase efficiency across our global engineering community.

Skills

ASIC/SoC design

RTL/Verilog

UVM/SystemVerilog

Verilog simulators

Synthesis/STA/DFT

Scripting: Perl/Python/Bash

Communication skills

BS/MS in EE/CS

Hands-on industry experience

Education

BS/MS in Electrical Engineering or CS

Tools

Verilog simulators

RTL/Verification linters

Clock-domain crossing checkers

Job description

Ericsson Silicon in Austin, Texas is seeking a Front-End CAD Infrastructure and Tools Engineer to shape the verification methodology and tools for SoC designs. You will lead tool flows, drive innovative design processes, and collaborate across design, verification, testing, and manufacturing teams to improve silicon design efficiency.

The role requires hands-on experience with ASIC/SoC design, RTL, Verilog, UVM, and SystemVerilog, plus scripting and regression tooling.