FPGA Design Verification Engineer (TS/SCI)

Inabia Software & Consulting Inc.; El Segundo (CA); On-site; USD 110,000 - 124,000; Full time

Job summary

Inabia Solutions & Consulting is seeking an experienced FPGA Design Verification Engineer to own verification activities from test planning through coverage closure and signoff. You will develop verification environments and validate hardware/software interactions with cross-functional teams.

The role requires 8–15 years of relevant experience, strong SystemVerilog/UVM skills, and the ability to manage verification independently while onsite in El Segundo, CA five days per week.

Qualifications

• 8–15 years of FPGA design verification experience.
• Strong SystemVerilog/UVM verification skills.
• Experience with C-based tests and HW/SW verification flows.
• Bachelor’s degree or equivalent in EE/CE/CS.
• U.S. citizenship required.
• Onsite work in El Segundo, CA five days per week.

Responsibilities

• Develop and maintain SystemVerilog/UVM testbenches, reusable UVCs, and automated tests.
• Create verification plans covering FPGA functionality, interfaces, and hardware/software interactions.
• Develop and integrate C-based tests, APIs, and software build flows.
• Implement mailbox mechanisms and communication components supporting hardware/software verification.
• Collect and analyze functional and code coverage, identify gaps, and drive coverage closure.
• Debug test failures, document defects, and collaborate with design and firmware engineers to resolve issues.
• Work with verification, architecture, design, and firmware teams to define verification scope and review results.
• Improve verification environments to increase defect detection and test efficiency.
• Own verification deliverables, communicate risks, and elevate issues when appropriate.
• Mentor junior engineers and participate in technical reviews.

Skills

SystemVerilog/UVM

C-based tests

Test planning

Code coverage

Debugging

Team collaboration

Mentoring

Education

Bachelor’s degree in Electrical/Computer Engineering or CS

Tools

UVCs

Job description

• FPGA Design Verification Engineer
• Employer: Inabia Solutions & Consulting Inc.
• Location: El Segundo, CA, onsite five days per week
• Employment Type: W-2 Contract
• Duration: 12 months
• Compensation: $80–$90per hour
• Work Authorization: U.S. citizenship required
• Clearance: DoD Secret clearance preferred

About the Role

Inabia Solutions & Consulting is seeking experienced FPGA Design Verification Engineers to own verification activities from test planning through coverage closure and final verification signoff. You will develop verification environments, validate hardware and software interactions, and work with architecture, design, and firmware teams to identify and resolve issues.

This role requires 8–15 years of relevant experience, strong hands‑on SystemVerilog/UVM skills, and the ability to manage verification responsibilities independently.

Responsibilities

• Develop and maintain SystemVerilog/UVM testbenches, reusable Universal Verification Components (UVCs), and automated tests.
• Create verification plans covering FPGA functionality, interfaces, and hardware/software interactions.
• Develop and integrate C-based tests, APIs, and software build flows.
• Implement mailbox mechanisms and communication components supporting hardware/software verification.
• Collect and analyze functional and code coverage, identify gaps, and drive coverage closure.
• Debug test failures, document defects, and collaborate with design and firmware engineers to resolve issues.
• Work with verification, architecture, design, and firmware teams to define verification scope and review results.
• Improve verification environments to increase defect detection and test efficiency.
• Own verification deliverables, communicate risks, and elevate issues when appropriate.
• Mentor junior engineers and participate in technical reviews.

Required Qualifications

• 8–15 years of relevant FPGA design verification experience.
• Strong understanding of FPGA devices and verification methodologies.
• Hands‑on experience developing SystemVerilog/UVM testbenches and reusable verification components.
• Experience developing C‑based tests and integrating hardware/software verification flows.
• Experience with test planning, functional and code coverage, debugging, and coverage closure.
• Ability to work independently and collaborate across engineering teams.
• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent relevant experience.
• U.S. citizenship required.
• Ability to work onsite in El Segundo, CA, five days per week.

Preferred Qualifications

• DoD Secret clearance.
• Experience verifying SpaceWire protocols.
• Experience with DDR4 memory interfaces.
• Experience with SerDes connectivity.
• Experience with configuration, control, and telemetry systems.