FPGA HDL Internship: Space Systems

Airbus Ventures; Austin (TX); Hybrid; USD 28,000 - 55,000; Full time

Benefits offered by this job

Onsite internship

Competitive compensation

Job summary

CesiumAstro is seeking Summer 2027 FPGA development interns to work on HDL-level FPGA systems for satellite communication systems. You will design, verification, testing, and deployment of HDL designs, handling high-speed interfaces, data streams, and digital processing cores.

Strong written and verbal communication are required. All internships are onsite at CesiumAstro facilities and compensated competitively.

Qualifications

• Currently enrolled in a BS/MS/PhD in Electrical or Computer Engineering.
• GPA 3.5 or higher.
• Advanced coursework in HDL design and FPGA systems.
• Practical FPGA design experience from projects, teams, or courses.
• Experience with Verilog/VHDL, Vivado, ModelSim, or similar tools.
• Hands-on lab experience with test equipment and measurements.

Responsibilities

• Develop HDL-level FPGA designs for satellite communication systems.
• Verify, test, and deploy HDL designs across multiple clock domains.
• Collaborate with CesiumAstro engineers across hardware and software teams.
• Present results and progress to mentors and leadership.

Skills

FPGA design

HDL design

Verilog/VHDL

Test & measurement

Strong communication

Education

BS in Electrical Engineering or Computer Engineering

MS or PhD in a relevant field

Tools

Vivado

ModelSim

Verilog

HDL Coder

Job description

CesiumAstro is seeking Summer 2027 FPGA development interns to work on HDL-level FPGA systems for satellite communication systems. You will design, verification, testing, and deployment of HDL designs, handling high-speed interfaces, data streams, and digital processing cores.

Strong written and verbal communication are required. All internships are onsite at CesiumAstro facilities and compensated competitively.