FPGA Engineer II: Space Hardware & HDL Verification

CesiumAstro, Inc.; Westminster (CO); Hybrid; USD 113,000 - 136,000; Full time

Benefits offered by this job

Stock options

Health insurance

Dental

Vision

HSA

FSA

Life insurance

Disability insurance

Retirement plans

Job summary

CesiumAstro, based in Westminster, Colorado, is seeking an FPGA Engineer II to design and verify FPGA systems for space and aerospace applications. You will contribute across all phases of the development lifecycle, focusing on HDL design, verification, and deployment to high‑speed interfaces and data paths.

The role requires strong FPGA expertise (Verilog/VHDL), hands‑on lab experience, and excellent communication.

Qualifications

• BS or MS in Electrical/Computer Engineering from an accredited university.
• Minimum of 2 years of industry experience in FPGA HDL design/analysis.
• Expertise in FPGA design and verification (Verilog/VHDL, HDL coder, Xilinx’s Vivado, Modelsim).
• Hands‑on experience with lab instruments such as digital oscilloscopes, spectrum analyzers, RF signal generators, and vector signal analyzers.
• Excellent written and verbal communication skills.

Responsibilities

• Develop FPGA circuits and systems through all development phases.
• HDL design, verification, and deployment at the HDL level.
• Handle high‑speed serial interfaces, data streams, and multiple clock domains.
• Conduct testing, validation, and verification as core tasks.
• Desirable: experience in digital signal processing or board‑level hardware design.

Skills

FPGA design

Verilog/VHDL

Vivado

ModelSim

Lab instruments

Communication skills

Education

BS or MS in Electrical/Computer Engineering

Tools

Vivado

ModelSim

HDL coder

Job description

CesiumAstro, based in Westminster, Colorado, is seeking an FPGA Engineer II to design and verify FPGA systems for space and aerospace applications. You will contribute across all phases of the development lifecycle, focusing on HDL design, verification, and deployment to high‑speed interfaces and data paths.

The role requires strong FPGA expertise (Verilog/VHDL), hands‑on lab experience, and excellent communication.