FPGA & Hardware Engineering Manager

OPSWAT, Inc.; Tampa (FL); On-site; USD 120,000 - 210,000; Full time

Job summary

OPSWAT, Inc. in Tampa, FL seeks an Engineering Manager to own the FPGA discipline for NetWall, leading RTL, verification, timing, and IP selection. You will drive the hardware datapath, coordinate with software, certification, QA, and manufacturing to deliver a secure gateway at line rate.

You will recruit senior FPGA engineers, set up build/regression infrastructure, and ensure Common Criteria/NCDSMO readiness while balancing timing, area, power, and cost across silicon families.

Qualifications

• Five+ years in FPGA development with shipping product RTL ownership.
• Leadership or management experience of FPGA engineers.
• Fluent in English; US person for security clearance.

Responsibilities

• Own the FPGA discipline for NetWall — RTL architecture, verification, timing, IP selection, and team development.
• Select silicon and boards; evaluate FPGA families and COTS cards for line rate and headroom; manage vendor relationships.
• Build the one-way datapath in gateware with no back-channel; ensure correct termination and re-origination.
• Move protocol termination into hardware — TCP state machines and TLS termination.
• Own verification as a deliverable — UVM environments, constrained-random, and coverage.
• Deliver design independence across two silicon lineages and toolchains; shared specs.

Skills

FPGA development leadership

SystemVerilog/VHDL

High-speed interfaces

RTL verification

Linux drivers/PCIe

AI-native working style

English communication

Tools

Vivado

Quartus Prime

Job description

OPSWAT, Inc. in Tampa, FL seeks an Engineering Manager to own the FPGA discipline for NetWall, leading RTL, verification, timing, and IP selection. You will drive the hardware datapath, coordinate with software, certification, QA, and manufacturing to deliver a secure gateway at line rate.

You will recruit senior FPGA engineers, set up build/regression infrastructure, and ensure Common Criteria/NCDSMO readiness while balancing timing, area, power, and cost across silicon families.