FPGA Functional Safety Engineer — RTL & ISO 26262

Tensor Auto; San Jose (CA); On-site; USD 75,000 - 300,000; Full time

Job summary

Tensor is seeking an experienced FPGA Safety Engineer to analyze and enhance safety for FPGA subsystems, ensure compliance with ISO 26262, and drive RTL design and verification across complex DSP-enabled FPGA pipelines.

The role requires 5+ years in FPGA development, Verilog/SystemVerilog proficiency, and hands-on experience with Xilinx toolchains and CPUs on Zynq platforms. Strong scripting and HDL skills are essential for this position in San Jose.

Qualifications

• Bachelor’s degree in Computer Engineering, Electrical Engineering, or related field.
• Minimum of 5 years of FPGA development experience, including HDL coding, simulation, test benches, synthesis, and timing closure.
• Solid understanding of safety principles and industry standards like ISO 26262 or ASIL-B.
• Advanced knowledge of RTL design using Verilog and SystemVerilog.
• Proficiency in scripting languages such as Python, TCL, Perl, or Bash.
• Hands‑on experience with embedded systems involving CPUs and FPGA platforms such as Xilinx Zynq devices.
• Experience with Xilinx and/or Intel FPGA toolchain.
• Experience with DSP algorithm implementations in FPGAs
• Knowledge of DDR4, AXI, I2C, UART, SPI, and Ethernet.

Responsibilities

• Conduct safety analysis for FPGA subsystems to ensure compliance with functional safety standards.
• Develop and maintain comprehensive functional safety documentation, including V-model requirements and FMEDA analysis.
• Design, implement, and integrate features within the FPGA stack, focusing on safety and reliability.
• Enhance and uphold FPGA development workflows to address functional safety requirements.
• Engage in FPGA development tasks, including RTL design, simulation, high-speed digital circuit design, DSP algorithm implementation, verification, synthesis, and timing analysis.
• Perform hands-on debugging and troubleshooting during board bring-up using laboratory equipment.
• Create automation scripts to streamline repetitive tasks, improving workflow efficiency and reliability.

Skills

HDL coding

RTL design

Python scripting

Embedded systems

Verilog/SystemVerilog

Education

Bachelor's degree in Electrical/Computer Engineering

Tools

Xilinx Zynq devices

Xilinx/Intel FPGA toolchain

Git

High-Level Synthesis (HLS) tools

Job description

Tensor is seeking an experienced FPGA Safety Engineer to analyze and enhance safety for FPGA subsystems, ensure compliance with ISO 26262, and drive RTL design and verification across complex DSP-enabled FPGA pipelines.

The role requires 5+ years in FPGA development, Verilog/SystemVerilog proficiency, and hands-on experience with Xilinx toolchains and CPUs on Zynq platforms. Strong scripting and HDL skills are essential for this position in San Jose.