FPGA/ASIC Design Engineer – Space, TS/SCI Eligible

Lockheed Martin; Boulder (CO); On-site; USD 136,000 - 252,000; Full time

Benefits offered by this job

Medical, Dental, Vision

Flexible work arrangements

401(k) match

Paid time off

Holidays

Parental Leave

EAP

Flexible Spending Accounts

Education Assistance

Life Insurance

Short-Term Disability

Long-Term Disability

Job summary

Lockheed Martin Space is seeking an FPGA Design Engineer to advance space-based mission processing at the edge. The role focuses on deploying processing code onto flight hardware using Vivado and HDL (VHDL/Verilog) and collaborating with research scientists, software engineers, and other FPGA engineers on the APEX team.

The selected candidate will translate mission processing C++ concepts to hardware, develop and test processor subsystems, and generate FPGA requirements and test benches.

Qualifications

• Bachelor of Science or higher from an accredited college in Electrical Engineering, Computer Engineering or related discipline, or equivalent experience/combined education.
• Ability to obtain a TS/SCI Clearance required for this role.
• Understanding of HDL Languages (VHDL & Verilog)
• Experience designing with Vivado

Responsibilities

• develop an understanding of mission processing code written in C++ and implement for hardware processing.
• develop, integrate, and test of processor subsystem features and interfaces in FPGA hardware.
• generate requirements, create FPGA code, and test bench development.

Skills

MATLAB

C++

Digital logic design

FPGA interfacing with processors

Education

B.S. in Electrical Engineering or Computer Engineering

Tools

Vivado

VHDL

Verilog

Xilinx platforms and tools

Vitis Model Composer

MATLAB HDL Coder

Job description

Lockheed Martin Space is seeking an FPGA Design Engineer to advance space-based mission processing at the edge. The role focuses on deploying processing code onto flight hardware using Vivado and HDL (VHDL/Verilog) and collaborating with research scientists, software engineers, and other FPGA engineers on the APEX team.

The selected candidate will translate mission processing C++ concepts to hardware, develop and test processor subsystems, and generate FPGA requirements and test benches.