ASIC & FPGA Design Engineer Sr

Lockheed Martin; Boulder (CO); On-site; USD 110,000 - 205,000; Full time

Benefits offered by this job

Flexible work arrangements

401(k) match

Paid time off

Holidays

Parental Leave

Job summary

Lockheed Martin Space in Boulder, Colorado, seeks a Field Programmable Gate Array (FPGA) Design Engineer to advance space-based mission processing and onboard flight hardware implementations. You will leverage Vivado, Vitis/HLS, and HDL (VHDL/Verilog) to deploy processing code and algorithms on flight hardware.

The role collaborates with researchers, software engineers, and fellow FPGA engineers on the APEX team, with focus on edge processing and ground-to-flight transitions.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering or related discipline, or equivalent experience.
• Ability to obtain TS/SCI Clearance.
• Understanding HDL languages (VHDL & Verilog).
• Experience designing with Vivado.

Responsibilities

• Develop understanding of mission processing code written in C++ for hardware processing.
• Develop, integrate, and test processor subsystem features and interfaces in FPGA hardware.
• Generate requirements, create FPGA code, and test bench development.
• Contribute to FPGA development workflows using both RTL and High-Level Synthesis within Vitis.

Skills

Digital logic design

Embedded software

FPGA interfacing

Matlab

C++

Education

Bachelor's degree in Electrical or Computer Engineering or related field

Tools

Vivado

Vitis

HDL (VHDL/Verilog)

High-Level Synthesis

Job description

Standard Job Description

Develops, designs, verifies, and documents Application-Specific Integrated Circuits (ASIC) and Field Programmable Gate Arrays (FPGA) development. Determines architecture design, logic design, and system simulation. Assignments include the analysis of all aspects from high-level design to synthesis, place and route, and timing and power utilization. Typically uses specialized equipment to establish operation data, conduct experimental tests, and evaluate results.

Standard Job Description

Develops, designs, verifies, and documents Application-Specific Integrated Circuits (ASIC) and Field Programmable Gate Arrays (FPGA) development. Determines architecture design, logic design, and system simulation. Assignments include the analysis of all aspects from high-level design to synthesis, place and route, and timing and power utilization. Typical uses specialized equipment to establish operation data, conduct experimental tests, and evaluate results.

Lockheed Martin Space is seeking a Field Programmable Gate Array (FPGA) Design Engineer to work on space-based mission processing capabilities at the edge. This position will help our team evolve ground-based mission processing applications of remote sensing payloads onto flight hardware for onboard mission processing operations. In this role, the FPGA Design Engineer will be responsible for leveraging the Vivado Design Suite, the Vitis development platform (including High-Level Synthesis), and hardware design languages VHDL and Verilog to deploy processing code and algorithms onto flight hardware. This position will work alongside research scientists, software engineers, and other FPGA engineers on the APEX (Advanced Programs and Exploitation) team.

The Selected Candidate Will Be Expected To

• develop an understanding of mission processing code written in C++ and implement for hardware processing.
• develop, integrate, and test processor subsystem features and interfaces in FPGA hardware.
• generate requirements, create FPGA code, and test bench development.
• contribute to FPGA development workflows using both traditional RTL design and High-Level Synthesis (HLS) methodologies within the Vitis platform.

Applicants selected will be subject to a government security investigation and must meet eligibility requirements for access to classified information.

This position is in beautiful Boulder, Colorado at our offices which have a collaborative and modern agile workspace.

Basic Qualifications

• Bachelor of Science or higher from an accredited college in Electrical Engineering, Computer Engineering or related discipline, or equivalent experience/combined education.
• Ability to obtain a TS/SCI Clearance required for this role.
• Understanding of HDL Languages (VHDL & Verilog).
• Experience designing with Vivado.

Desired Skills

• Experience with Xilinx Vitis platform, including High-Level Synthesis (HLS) for FPGA development
• Proficient in Matlab & C++
• Digital logic design experience
• Experience interfacing FPGAs with processors
• Experience with Vitis Model Composer
• Experience with Matlab HDL Coder
• Familiarity with Xilinx platforms and tools
• Knowledge of FPGA concepts like clock domains, memory hierarchies, and routing
• Experience with embedded software development
• Familiarity with embedded Linux environments (e.g., Yocto)

Pay Information

Full-Time Salary Range: $110300.00 - $204900.00

At Lockheed Martin, we know mission success starts with taking care of our people. Our Total Rewards program is designed to attract top talent, support your well-being, and help you grow—both professionally and personally.

The salary range for this position is as listed on the requisition. Please note that the salary information listed is a general guideline only. Lockheed Martin considers factors such as (but not limited to) scope and responsibilities of the position, candidate's work experience, education/ training, key skills as well as market(work location) and business considerations when extending an offer.

Benefits offered:

Medical, Dental, Vision, Flexible work arrangements and schedules (e.g., 4x10), 401(k) match, Paid time off, Holidays, Parental Leave, EAP, Flexible Spending Accounts, Education Assistance, Life Insurance, Short-Term Disability, and Long-Term Disability.

• Annual short-term and/or long-term incentive compensation programs may be offered depending on the position. Payments under these annual programs are not guaranteed and can vary from year to year and are tied to a range of performance metrics.
• For (Washington state applicants only) Non-represented full-time employees: accrue at least 10 hours per month of Paid Time Off (PTO) to be used for incidental absences and other reasons; receive at least 90 hours for holidays. Represented full time employees accrue 6.67 hours of Vacation per month; accrue up to 52 hours of sick leave annually; receive at least 96 hours for holidays. PTO, Vacation, sick leave, and holiday hours are prorated based on start date during the calendar year.