Design Verification Lead

TYLsemi; United States; Remote; USD 180,000 - 240,000; Full time

Job summary

TYLsemi is seeking a Design Verification Lead to define and execute scalable verification strategies for next-generation AI, HPC, and Networking SoCs. You will drive architecture from IP to full chip, building reusable platforms and employing AI-driven methodologies.

You will mentor DV teams, collaborate with design, physical design, and software, and push for first-pass silicon success through automation, high-coverage testbenches, and cross-level stimulus reuse.

Qualifications

• Bachelor’s/Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of experience in Design Verification, with large SoC verification.
• Proven experience defining and deploying verification architectures for complex chips.
• Strong expertise in SystemVerilog and UVM.
• Coverage-driven verification (functional + code coverage).
• Assertion-based verification (SVA).
• Experience with Portable Stimulus (PSS) and cross-level stimulus reuse.
• Experience with industry-standard protocols (PCIe, DDR, Ethernet, CXL, UCIe).
• Deep understanding of SoC architectures in AI, HPC, or Networking domains.
• Experience with multi-IP integration challenges, coherency, high-speed interfaces, and large-scale data movement.
• Strong debugging skills and ability to handle complex system-level issues.

Responsibilities

• Define and drive the overall verification architecture for large-scale SoCs, ensuring scalability from IP to subsystem to full SoC level.
• Architect and develop reusable, modular, and portable verification platforms that can be leveraged across multiple chip programs.
• Establish methodologies for seamless reuse and portability, including Portable Stimulus (PSS)-based verification flows.
• Lead the development of high-performance, coverage-driven testbenches using industry-standard methodologies (e.g., UVM).
• Drive multi-level verification strategies, enabling efficient scaling across Block-level, Multi-block/subsystem level, Full-chip SoC level.
• Define and enforce verification quality metrics, coverage closure strategies, and sign-off criteria.
• Champion a fail-fast philosophy to detect issues early and improve overall design quality.
• Drive initiatives toward first-pass silicon success, minimizing escapes and post-silicon debug effort.
• Leverage AI/ML techniques and AI agents to automate testbench generation, improve stimulus generation and coverage closure, and enhance regression efficiency.
• Enable intelligent verification QA and anomaly detection.
• Collaborate closely with design, architecture, physical design, and software teams to ensure alignment and early issue detection.
• Mentor and guide DV teams on best practices, methodology adoption, and architectural decisions.

Skills

SystemVerilog

UVM

SVA

Portable Stimulus

Testbench automation

AI-driven verification

SoC architecture

Multi-IP integration

Debugging

Architecture leadership

Education

Bachelor’s/Master’s in Electrical Engineering or Computer Engineering

Tools

PCIe

DDR

Ethernet

CXL

UCIe

Job description

Role Overview

We areseekinga highly experienced Design Verification Lead to lead the definition and execution of scalable, reusable, and high-quality verification strategies for next-generation SoCs targeting AI, HPC, and Networking applications. This role requires deepexpertisein verifying large and complex SoCs and a passion for building next-gen verificationplatforms,leveraging automation, portability, and AI-driven methodologies.

WhatYou'llDo

• Define and drive the overall verification architecture for large-scale SoCs, ensuring scalability from IP to subsystem to full SoC level
• Architect and develop reusable, modular, and portable verification platforms that can beleveragedacross multiple chip programs
• Establish methodologies for seamless reuse and portability , includingPortable Stimulus (PSS)-based verification flows
• Lead the development of high-performance, coverage-driven testbenches using industry-standard methodologies (e.g., UVM)
• Drive multi-level verification strategies , enabling efficient scaling across:
• Block-level, Multi-block/subsystem level, Full-chip SoC level
• Define and enforce verification quality metrics , coverage closure strategies, and sign-off criteria
• Champion a fail-fast philosophy to detect issues early and improve overall design quality
• Drive initiatives toward first-pass silicon success , minimizing escapes and post-silicon debug effort
• Leverage AI/ML techniques and AI agents to:
• Automate testbench generation
• Improve stimulus generation and coverage closure
• Enhance regression efficiency and debug productivity
• Enable intelligent verification QA and anomaly detection
• Collaborate closely with design, architecture, physical design, and software teams to ensure alignment and early issue detection
• Mentor and guide DV teams on best practices, methodology adoption, and architectural decisions

WhatWe'reLookingFor

• Bachelor’s/Master’s degree in Electrical Engineering, Computer Engineering, or related field
• 10+ years of experience in Design Verification , with significant exposure to large SoC verification
• Proven experience in defining and deploying verification architectures for complex chips
• Strongexpertisein:
• SystemVerilogand UVM
• Coverage-driven verification (functional + code coverage)
• Assertion-based verification (SVA)
• Hands-on experience withPortable Stimulus (PSS)and cross-level stimulus reuse
• Experience on industry-standard protocols (e.g., PCIe, DDR, Ethernet, CXL, UCIe)
• Deep understanding of SoC architectures in AI, HPC, or Networking domains
• Experience with multi-IP integration challenges , coherency, high-speed interfaces, and large-scale data movement
• Strong debugging skills and ability to handle complex system-level issues

Good to Have

• Experience with AI/ML applications in verification workflows
• Exposure to emulation, prototyping, or hybrid verification platforms
• Familiarity with performance verification and power-aware verification
• Knowledge of industry-standard protocols (e.g., PCIe, DDR, Ethernet, CXL, UCIe)
• Experience building verification frameworks reused across multiple tape-outs

Key Attributes

• Strong architectural thinking with a systems-level mindset
• High ownership with a quality-first approach
• Bias toward automation, reuse, and scalability
• Passion for adopting cutting-edge technologies , especially AI-driven verification
• Ability tooperatein a fast-paced environment with a fail-fast, learn-fast attitude
• Excellent collaboration and leadership skills

Success in This Role Looks Like

High degree of verification reuse across programs

Achievement of coverage and quality goals within schedule

Reduction in verification cycle time through automation and AI

Strongtrack recordof first-time silicon success

Minimal post-silicon escapes and debug cycles