Emulation Verification Engineer - Wireless SoCs

Apple Inc.; San Francisco (CA); On-site; USD 129,000 - 225,000; Full time

Benefits offered by this job

Apple Benefits

Relocation assistance

Employee stock programs

Job summary

Apple Inc. in the San Francisco Bay Area is seeking an Emulation Verification Engineer to join the emulation team focused on verification of large Wireless SoCs using Palladium and mixed-signal models.

You will port designs to Palladium, develop monitors, run test plans, and collaborate with Design, Architecture, Power, Silicon Validation, and SW teams; strong SystemVerilog/UVM skills required, bachelor's degree.

Qualifications

• Bachelor’s degree is required.
• Experience with SystemVerilog, Verilog or UVM.
• Experience with emulation bring-up and verification.

Responsibilities

• Work with the emulation team to bring up large Wireless SoCs on emulation platforms.
• Develop monitors and checkers for emulation verification.
• Prepare and execute test plans and review results with cross-functional teams.
• Collaborate with Design, Architecture, Power, Silicon Validation and SW teams.
• Develop verification code using SystemVerilog/UVM for emulation activities.

Skills

SystemVerilog

Verilog

UVM

C/C++ DPI

Scripting

Low Power UPF

UVM Acceleration

Emulation

Education

Bachelor's degree

Tools

Palladium

Veloce

Zebu

Xilinx

Altera

Job description

Apple Inc. in the San Francisco Bay Area is seeking an Emulation Verification Engineer to join the emulation team focused on verification of large Wireless SoCs using Palladium and mixed-signal models.

You will port designs to Palladium, develop monitors, run test plans, and collaborate with Design, Architecture, Power, Silicon Validation, and SW teams; strong SystemVerilog/UVM skills required, bachelor's degree.