Emulation Lead/Principal Engineer

TYLsemi; San Jose (CA); Hybrid; USD 238,000 - 286,000; Full time

Job summary

TYLsemi is hiring a Principal Engineer Emulation Lead to build scalable pre-silicon environments that boot real software and run workloads months before tapeout. You will architect full-chip emulation platforms and drive cross-domain validation across RTL, firmware, and software teams.

You'll own emulation platforms using Palladium/ZeBu/Veloce, lead complex debug, mentor engineers, and shape observability and release processes that scale across the organization.

Qualifications

• 10+ years in ASIC/SoC development with emulation ownership.
• Experience with Palladium, ZeBu or Veloce emulation platforms.
• Strong RTL skills in Verilog/SystemVerilog and firmware bring-up.
• Proficiency in C/C++ and Python scripting.
• Proven cross-functional debugging and technical leadership.

Responsibilities

• Architect and deploy full-chip, multi-die, and subsystem emulation environments.
• Enable pre-silicon bring-up of boot ROM, firmware, drivers, and OS.
• Develop scalable emulation methodologies and reusable infrastructure.
• Drive system-level validation, performance analysis, and root-cause debug.
• Build automation, CI/CD workflows, regressions, and release processes.
• Partner with multiple teams to reduce product risk before tapeout.
• Influence observability, debugability, and silicon readiness.
• Lead complex debug spanning RTL, firmware, software, and hardware.
• Mentor engineers and shape architecture for better diagnostics.

Skills

RTL Verilog/SV

Firmware bring-up

C/C++

Python scripting

Cross-functional leadership

Emulation ownership

Tools

Palladium

ZeBu

Veloce

Job description

Role Overview

tapeout.

Role Overview

Build the platform that brings silicon to life before tapeout. TYLsemi is developing purpose-built connectivity chiplet for HPC/rack-scale AI systems. We are seeking a Principal Engineer Emulation Lead to create scalable pre-silicon environments that enable firmware, software, and system validation months before first silicon arrives. You'll build production-grade platforms that boot real software, run meaningful workloads, expose system bottlenecks, and accelerate product readiness across the organization.

What You'll Do

• Architect and deploy full-chip, multi-die, and subsystem emulation environments using Palladium, ZeBu, Veloce, or similar platforms.
• Enable pre-silicon bring-up of boot ROM, firmware, drivers, operating systems, and application workloads.
• Develop scalable emulation methodologies and reusable infrastructure,
• Drive system-level validation, performance analysis, and root-cause debug across RTL, firmware, software, and verification.
• Build automation, CI/CD workflows, regressions, and release processes that scale across engineering teams.
• Partner with architecture, design, verification, firmware, DFT, and post-silicon teams to reduce product risk before tapeout.
• Influence methodology, observability, debugability, and overall silicon readiness.
• Lead complex debug spanning RTL, firmware, software, and hardware platforms.
• Mentor engineers and influence architecture to improve observability, diagnosability, and product quality.

What We're Looking For

• 10+ years of ASIC/SoC development experience with significant emulation ownership.
• Expertise with commercial emulation platforms (Palladium, ZeBu, or Veloce).
• Strong RTL skills in Verilog/SystemVerilog.
• Experience with firmware bring-up, embedded processors, interrupts, and system debug.
• Proficiency in C/C++ and scripting with Python.
• Excellent cross-functional debugging and technical leadership skills.
• Proven track record leading complex verification and emulation programs.

Good to Have

• Ethernet, PCIe, CXL or high-speed interconnects.
• FPGA prototyping (Protium, HAPS, etc.).
• Security architectures, Root of Trust, and secure boot.
• First-silicon bring-up and system qualification experience.

Success in This Role Looks Like

• The emulation platform reliably boots target firmware/OS and runs representative workloads well ahead of tapeout, giving firmware and software teams real hardware behavior months earlier than post-silicon would allow.
• Emulation infrastructure (CI/CD, regressions, release process) is stable enough that other engineering teams can self-serve without heavy hand-holding.
• Cross-functional debug cycles (RTL/firmware/software) shrink because observability and diagnosability were built into the platform, not bolted on after issues surface.
• Design and firmware teams treat the emulation lead as a trusted escalation point for hard-to-reproduce, cross-domain bugs.

Compensation

The compensation range shown below represents total target cash compensation and includes both base salary and target bonus. Actual compensation will vary based on factors such as experience, skills, qualifications, job level, and work location.

In addition to cash compensation, this position is eligible for equity in the form of stock options, giving you the opportunity to share in the Company’s long-term growth and success.

About TYLsemi, Inc.

The Opportunity

The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package? That's what we solve. TYLsemi builds the chiplet infrastructure IP — the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale.

This isn't a nice-to-have. It's the critical path.

Why Now

The Market Window

• Moore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.
• Custom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI — they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually.
• IO and power are the bottleneck. Solve hard problems and provide something which is a category in itself.
• Translation: We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.

Culture & Team: How We Work

No Politics, No Bureaucracy

There are no layers, no approval chains, no corporate theater.

• If you have an idea, we test it. If it works, we ship it.
• No endless meetings, no PowerPoint presentations to convince middle management.

Remote-Friendly, Global Team

• US team: Bay Area preferred, but we hire the best people regardless of location
• India team: Building a world-class design center in Bangalore

Move Fast, Ship Real Products

We're not a research project. We have paying customers, committed capital, and aggressive timelines.

This is a company, not a lifestyle business. We're building to win.

What We Value

• Ownership mindset. You're not here to execute someone else's roadmap. You're here to define it.
• Bias for action. We move fast. Analysis paralysis doesn't fly here.
• Deep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware.
• Low ego, high standards. We don't care about titles or politics. We care about results.

The Ask

If you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits.

We're asking you to walk away from that and bet on us.

Here's Why You Should

• The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building.
• The team has done this before. We've built and exited semiconductor companies at scale. This isn't our first rodeo.
• The traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue.
• The work is consequential. You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI.

This is the bet.

Join us and build something that matters.

Or stay comfortable. No judgment.

But if you're the kind of person who wants to take the shot, we'd love to talk.

READY TO JOIN?

The Pay Range For This Role Is

237,500 - 286,000 USD per year (US)