Lead SoC Design Verification (DV) Engineer

TylSemi; San Jose (CA); Remote; USD 180,000 - 240,000; Full time

Benefits offered by this job

Stock options

Remote-friendly team

Job summary

TYLsemi seeks a seasoned SoC Design Verification Lead to architect and drive verification strategy for next-generation semiconductor products. You will lead a team of verification engineers, defining testbenches, regressions, and automation to ensure first-time-right silicon.

You will collaborate with Front-End, Emulation, and Firmware teams, applying formal methods, SVA, AI-driven techniques, and advanced DV to validate complex blocks, subsystems, and full-chip fabrics.

Qualifications

• 12+ years of hardware verification experience with tape-out success on complex SoCs.
• Master-level proficiency in SystemVerilog and UVM.
• Deep expertise in constrained-random verification, functional coverage, and SVA.
• Experience with major EDA simulators and debug platforms.
• Strong analytical and cross-functional communication skills.

Responsibilities

• Lead, mentor, and grow the verification team; architect the verification environment.
• Translate architectures into comprehensive verification plans and stress test edge cases.
• Own environment architecture using SystemVerilog and UVM; deploy AI-driven methods.
• Apply formal verification, SVA, and HW/SW co-verification where beneficial.
• Oversee IP and SoC verification, including power, clocking, and security features.
• Track coverage and sign-off criteria; coordinate with Front-End and Post-Silicon teams.

Skills

SystemVerilog

UVM

Constrained-random verif.

Formal verification

SVA

Leadership

Education

Bachelor’s or Master’s in Electrical/Computer Engineering, CS

Tools

Cadence

Synopsys

Mentor Graphics

Emulation platforms

Job description

Role Overview

We are seeking an analytical and strategic SoC Design Verification (DV) Lead to architect, drive, and execute the verification strategy for our next-generation semiconductor products. In this role, you will lead a team of verification engineers tasked with validating highly complex, multi-million gate SoC designs. You will work side-by-side with the SoC Front-End Lead and cross functional teams including Emulation and Firmware teams to establish robust methodologies and guarantee first-time-right silicon through rigorous block-level, subsystem, and full-chip verification.

What you'll do

• Technical Leadership & DV Strategy: Lead, mentor, and grow the verification team. Architect the overall verification environment, defining the standards for testbenches, automation scripts, and regression metrics.
• Verification Planning: Translate architectural specifications into comprehensive verification plans. Identify edge cases, corner cases, and critical scenarios that must be stress-tested.
• Environment Architecture (UVM): Own and build modular, scalable, and reusable advanced verification environments using SystemVerilog and Universal Verification Methodology (UVM).
• Deploy AI-driven verification methodology for SoC Verification.
• Advanced Verification Techniques: Deploy formal verification, assertion-based verification (SVA), and hardware/software co-verification where appropriate to accelerate bug discovery.
• IP & SoC Verification: Manage verification at all levels—from complex customized internal blocks to standard third-party IPs and full-chip fabrics. Ensure proper validation of critical system features like power management (UPF), clocking/resets, and security features.
• Signoff Discipline: Track and drive functional coverage, code coverage, and assertion metrics to absolute closure. Define and enforce the official bug-bar and criteria for pre-silicon signoff.
• Cross-Functional Collaboration: Partner directly with the Front-End Design Lead to resolve complex RTL bugs. Coordinate with Emulation and Post-Silicon validation teams to cleanly hand off test suites and debug insights.

What We're Looking For

• Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• Experience: 12+ years of hardware verification experience, with a proven history of tape-out success on complex, large-scale SoCs.
• Methodology Expertise: Master-level proficiency in SystemVerilog and UVM.
• Technical Skills: Deep expertise in constrained-random verification, functional coverage model design, and writing complex SystemVerilog Assertions (SVA).
• Tools: Expert familiarity with major EDA simulator and debug platforms.
• Soft Skills: Strong analytical problem-solving skills and excellent cross-functional communication to balance verification thoroughness with strict project timelines.

Good to Have

• Experience using Formal Verification methodologies to verify complex control logic.
• Hands-on experience with hardware emulation platforms for speed-up or OS-booting.
• Strong proficiency in scripting to manage continuous integration (CI/CD) and automated regression triage.

Compensation

The compensation range shown below represents total target cash compensation and includes both base salary and target bonus. Actual compensation will vary based on factors such as experience, skills, qualifications, job level, and work location.

In addition to cash compensation, this position is eligible for equity in the form of stock options, giving you the opportunity to share in the Company’s long-term growth and success.

About TYLsemi, Inc.

The Opportunity

The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?

That's what we solve. TYLsemi builds the chiplet infrastructure IP — the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale.

This isn't a nice-to-have. It's the critical path.

Why Now

The Market Window

The semiconductor industry is going through its biggest architectural shift in 40 years:

• Moore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.
• Custom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI — they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually.
• IO and power are the bottleneck. Solve hard problems and provide something which is a category in itself.
• Translation: We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.

Culture & Team: How We Work

No Politics, No Bureaucracy

There are no layers, no approval chains, no corporate theater.

• If you have an idea, we test it. If it works, we ship it.
• No endless meetings, no PowerPoint presentations to convince middle management.

Remote-Friendly, Global Team

• US team: Bay Area preferred, but we hire the best people regardless of location
• India team: Building a world-class design center in Bangalore

Move Fast, Ship Real Products

We're not a research project. We have paying customers, committed capital, and aggressive timelines.

This is a company, not a lifestyle business. We're building to win.

What We Value

• Ownership mindset. You're not here to execute someone else's roadmap. You're here to define it.
• Bias for action. We move fast. Analysis paralysis doesn't fly here.
• Deep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware.
• Low ego, high standards. We don't care about titles or politics. We care about results.

The Ask

If you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits.

We're asking you to walk away from that and bet on us.

Here's why you should:

• The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building.
• The team has done this before. We've built and exited semiconductor companies at scale. This isn't our first rodeo.
• The traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue.
• The work is consequential. You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI.

This is the bet. Join us and build something that matters.

Or stay comfortable. No judgment.

But if you're the kind of person who wants to take the shot, we'd love to talk.