Lead SoC Performance & Power Engineer

TYLsemi; San Jose (CA); Remote; USD 204,000 - 250,000; Full time

Job summary

TYLsemi, Inc. is seeking a Lead Performance Architect to drive architectural configuration, system-level simulation, and PPA optimization for chiplet integration including PCIe, UCIe, and NoC IPs.

You will own trade-off analyses that determine what gets taped out and work with ESL tools to model full-chiplet behavior. Qualifications include 6+ years in computer architecture, hands-on ESL tool experience, and strong Python and SystemC skills.

Qualifications

• BS/MS in Electrical Engineering or related field with 6+ years in computer architecture or performance modeling.
• Hands-on experience with ESL tools such as Platform Architect or Virtualizer.
• Strong knowledge of PCIe, UCIe, or AMBA NoC protocols; willing to learn others.
• Python scripting for automating large-scale simulations.
• Familiarity with SystemC and transaction-level modeling.

Responsibilities

• Own PPA exploration and tape-out trade-offs.
• Build TLMs using ESL suites to integrate IPs into a full-chiplet model.
• Define and validate hardware configuration parameters to maximize throughput.
• Characterize NoC/UCIe traffic to find congestion points.
• Collaborate with IP vendors to debug models and land new IP.

Skills

PPA optimization

System-level modeling

Python scripting

SystemC modeling

ESL tools

Traffic generators

IP integration

Education

BS in Electrical Engineering

MS in Electrical Engineering

Tools

Platform Architect

Virtualizer

SystemC

Job description

About The Role

As our Lead Performance architect, you'll drive the architectural configuration, system-level simulation, and PPA optimization of the chiplet by using industry-standard ESL tools and / or developing in-house tools to integrate and calibrate highspeed I/O IPs such as PCIe, UCIe and Ethernet as well as NoC fabric into a system. You'll own the trade-off analysis that define what we tape out.

Responsibilities

• Own PPA exploration and trade-offs between peak performance, silicon area, and thermal/power budgets, and turn that into clear tape-out recommendations.
• Build transaction-level models (TLM) using commercial ESL suites (e.g. Platform Architect) that integrate third-party IPs such as PCIe, UCIe, and NoC etc into a full-chiplet model.
• Define, sweep, and validate hardware configuration parameters — buffer sizes, queue depths, clock-domain crossings, routing tables — to maximize throughput and minimize latency across realistic workloads.
• Characterize traffic across the internal NoC and the UCIe die-to-die interface to find congestion points and rule out protocol deadlocks before they reach silicon.
• Work directly with our IP vendors to debug model/behavioral mismatches, report performance anomalies, and integrate new IP deliverables as they land.

Required

• BS/MS in Electrical Engineering or related field with 6+ years in computer architecture, performance modeling, or microarchitecture configuration.
• Direct, hands-on experience with commercial ESL tools such as Platform Architect, Virtualizer, or comparable frameworks.
• Solid working knowledge of at least one of: PCIe (Gen 5/6/7), UCIe, or AMBA NoC protocols (AXI/CHI) — and a willingness to get deep on the others.
• Strong Python for automating large-scale simulation sweeps, parsing performance reports, and analyzing results.
• Familiarity with SystemC and transaction-level modeling paradigms — enough to write custom traffic generators when the off-the-shelf models fall short.

Nice to have

• Fluency with power modeling or floor-planning trade-offs.
• Prior work on a multi-die / chiplet program, or hands-on UCIe die-to-die.
• Experience taking architectural models through to a real tape-out.

Compensation

The compensation range shown below represents total target cash compensation and includes both base salary and target bonus. Actual compensation will vary based on factors such as experience, skills, qualifications, job level, and work location.

In addition to cash compensation, this position is eligible for equity in the form of stock options, giving you the opportunity to share in the Company’s long‑term growth and success.

About TYLsemi, Inc.

The Opportunity

The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package? That's what we solve. TYLsemi builds the chiplet infrastructure IP — the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale.

This isn't a nice-to-have. It's the critical path. Why Now

The Market Window

• Moore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.
• Custom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI — they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually.
• IO and power are the bottleneck. Solve hard problems and provide something which is a category in itself.
• Translation: We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.

Culture & Team: How We Work

No Politics, No Bureaucracy

There are no layers, no approval chains, no corporate theater.

• If you have an idea, we test it. If it works, we ship it.
• No endless meetings, no PowerPoint presentations to convince middle management.

Remote-Friendly, Global Team

• US team: Bay Area preferred, but we hire the best people regardless of location
• India team: Building a world-class design center in Bangalore

Move Fast, Ship Real Products

We're not a research project. We have paying customers, committed capital, and aggressive timelines.

This is a company, not a lifestyle business. We're building to win.

What We Value

• Ownership mindset. You're not here to execute someone else's roadmap. You're here to define it.
• Bias for action. We move fast. Analysis paralysis doesn't fly here.
• Deep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware.
• Low ego, high standards. We don't care about titles or politics. We care about results.

The Ask

If you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits.

We're asking you to walk away from that and bet on us.

Here's Why You Should

• The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building.
• The team has done this before. We've built and exited semiconductor companies at scale. This isn't our first rodeo.
• The traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue.
• The work is consequential. You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI.

This is the bet. Join us and build something that matters. Or stay comfortable. No judgment. But if you're the kind of person who wants to take the shot, we'd love to talk.

READY TO JOIN?

The Pay Range For This Role Is

204,000 - 250,000 USD per year (US)