Early-Career Design Engineer - Hardware & Verification

Silicon Labs; Austin (TX); On-site; USD 80,000 - 120,000; Full time

Job summary

Silicon Labs, headquartered in Austin, Texas, is building an early-career talent pool for Design Engineering teams across Analog/Mixed-Signal, Digital Design, Verification, Physical Design/Layout, RF, and CAD.

Ideal candidates will graduate Dec 2026 or May 2027 and have coursework or internships in semiconductor design/verification, with exposure to Verilog, SystemVerilog, VHDL, UVM, Python, C/C++, MATLAB, Cadence, Synopsys or Siemens EDA.

Qualifications

• Graduation date Dec 2026 or May 2027 or later, in a relevant technical field.
• Coursework, research or internship in semiconductor design or verification.
• Exposure to analog or digital circuits, RTL design, verification, or RF systems.
• Hands-on experience with Verilog/SystemVerilog/VHDL/UVM or related tools.

Responsibilities

• Collaborate with design teams across analog/mixed-signal and digital design.
• Support verification, layout, and design automation initiatives.
• Assist in evaluating and testing semiconductor designs and flows.
• Contribute to problem solving and debugging across projects.

Skills

Analytical thinking

Problem-solving

Debugging

Clear communication

Team collaboration

Education

Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, Computer Science, Microelectronics, or related technical field

Tools

Verilog

SystemVerilog

VHDL

UVM

Python

C/C++

MATLAB

Cadence

Synopsys

Siemens EDA

Job description

Silicon Labs, headquartered in Austin, Texas, is building an early-career talent pool for Design Engineering teams across Analog/Mixed-Signal, Digital Design, Verification, Physical Design/Layout, RF, and CAD.

Ideal candidates will graduate Dec 2026 or May 2027 and have coursework or internships in semiconductor design/verification, with exposure to Verilog, SystemVerilog, VHDL, UVM, Python, C/C++, MATLAB, Cadence, Synopsys or Siemens EDA.