DTCO Intern: DRAM Physical Design & PPA Optimization

Micron Technology, Inc; Boise, Northern (ID, KY); Hybrid; USD 2,755,000 - 4,959,000; Full time

Job summary

Micron Technology, Inc. invites applications for an Intern in DRAM Technology Physical Design and Block-Level PPA Optimization in Boise, Idaho. The role focuses on implementing standard cell blocks, benchmarking PPA, and supporting timing closure using industry tools and AI-enabled automation.

You will gain hands-on experience in physical design, timing analysis, and design verification while collaborating with DTCO teams to optimize silicon outcomes and power efficiency.

Qualifications

• Currently pursuing a B.S. or M.S. degree in Electrical Engineering, Computer Engineering, or a related technical field.
• Experience with VLSI design concepts, CMOS circuits, digital logic, and the ASIC physical design flow.
• Proficiency in scripting languages (Python, Perl, TCL) for automation.

Responsibilities

• Implement standard cell logic blocks using industry-standard physical design tools (floorplanning, placement, CTS, routing, PPA optimization).
• Analyze and benchmark PPA across standard cell libraries and configurations to identify improvements.
• Perform STA, investigate timing violations, and support timing closure; conduct DRC/LVS/IR-drop checks and assist issue resolution.

Skills

Python

Perl

TCL

Education

B.S./M.S. in Electrical Engineering or Computer Engineering

Tools

Synopsys ICC2

Cadence Innovus

Job description

Micron Technology, Inc. invites applications for an Intern in DRAM Technology Physical Design and Block-Level PPA Optimization in Boise, Idaho. The role focuses on implementing standard cell blocks, benchmarking PPA, and supporting timing closure using industry tools and AI-enabled automation.

You will gain hands-on experience in physical design, timing analysis, and design verification while collaborating with DTCO teams to optimize silicon outcomes and power efficiency.