DTCO Intern: AI-Driven PPA & Layout Optimization for DRAM

Micron; Boise (ID); On-site; USD 30,000 - 42,000; Full time

Benefits offered by this job

Medical benefits

Dental benefits

Vision benefits

Paid time off

Paid holidays

Job summary

Micron Technology is seeking a DTCO Intern to gain hands-on experience optimizing power, performance, and area at the standard cell and logic block level. You will use industry-standard place-and-route tools and AI-enabled automation to benchmark and improve silicon outcomes.

As part of the internship, you will perform timing analysis, physical verification, and data-driven workflow enhancements while learning the ASIC design flow.

Qualifications

• Pursuing a B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
• Understanding of VLSI design concepts, CMOS circuits, digital logic, and ASIC physical design flow.
• Experience with scripting languages (Python, Perl, or TCL) through coursework or projects.

Responsibilities

• Implement standard cell logic blocks using industry-standard physical design tools (floorplanning, placement, CTS, routing).
• Analyze and benchmark PPA across libraries and configurations to identify improvements.
• Perform STA, investigate timing violations, and support timing closure.
• Execute DRC, LVS, and IR-drop analysis to resolve design issues.
• Leverage Generative AI and AI-assisted tools to automate data collection and workflow optimization for PPA analysis.

Skills

VLSI concepts

Scripting (Python, Perl, TCL)

Analytical problem solving

Timing closure understanding

Education

B.S. or M.S. in Electrical/Computer Engineering or related field

Tools

Synopsys ICC2

Cadence Innovus

PrimeTime/Tempus

SDC/LEF/DEF

Job description

Micron Technology is seeking a DTCO Intern to gain hands-on experience optimizing power, performance, and area at the standard cell and logic block level. You will use industry-standard place-and-route tools and AI-enabled automation to benchmark and improve silicon outcomes.

As part of the internship, you will perform timing analysis, physical verification, and data-driven workflow enhancements while learning the ASIC design flow.