DTCO Intern: PPA Optimization for DRAM Logic Blocks

Micron Technology, Inc; Boise (ID); On-site; USD 25,000 - 40,000; Part time

Job summary

Micron Technology, Inc. invites applications for a DTCO Intern role in Boise, Idaho. You will gain hands-on experience assessing and optimizing PPA at the standard cell and logic block level using industry tools and AI-enabled automation.

Primary focus includes implementing standard cell logic blocks, analyzing power, performance, and area, and supporting timing closure and physical verification tasks. A strong foundation in VLSI concepts and scripting is required.

Qualifications

• Pursuing a B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
• Strong understanding of VLSI design concepts, CMOS circuits, digital logic, and the ASIC physical design flow.
• Experience using scripting languages such as Python, Perl, or TCL.

Responsibilities

• Implement standard cell logic blocks using industry‑standard physical design tools, including floorplanning, placement, CTS, routing, and optimization for PPA.

Skills

Python

Perl

TCL

analytical skills

debugging skills

Education

B.S. or M.S. in Electrical/Computer Engineering

Tools

Synopsys ICC2

Cadence Innovus

PrimeTime

Job description

Micron Technology, Inc. invites applications for a DTCO Intern role in Boise, Idaho. You will gain hands-on experience assessing and optimizing PPA at the standard cell and logic block level using industry tools and AI-enabled automation.

Primary focus includes implementing standard cell logic blocks, analyzing power, performance, and area, and supporting timing closure and physical verification tasks. A strong foundation in VLSI concepts and scripting is required.