DTCO Intern: PPA Optimization for Standard Cells

Micron Technology; Boise (ID); On-site; USD 42,000 - 64,000; Full time

Benefits offered by this job

Medical, dental, vision plans

Paid time off

Paid holidays

Job summary

Micron Technology is seeking a DTCO Intern to gain hands‑on experience optimizing power, performance, and area for memory products. You will work on standard cell logic, use industry tools for floorplanning, CTS, placement, routing, and timing closure, and analyze PPA across libraries and configurations.

You will apply AI-assisted methods to automate data collection, reporting, and workflow optimization while developing skills in physical design and timing analysis.

Qualifications

• Currently pursuing a B.S. or M.S. degree in Electrical Engineering, Computer Engineering, or a related technical field.
• Demonstrated understanding of VLSI design concepts, CMOS circuits, digital logic, and the ASIC physical design flow.
• Experience through coursework, research, or projects using scripting languages such as Python, Perl, or TCL.
• Strong analytical, problem-solving, and debugging skills with attention to technical detail.
• Expected graduation date of Fall 2025 or later.

Responsibilities

• Implement standard cell logic blocks using industry-standard physical design tools, including floorplanning, placement, clock tree synthesis (CTS), routing, and optimization activities focused on PPA assessment.
• Analyze and benchmark power, performance, and area across standard cell libraries and logic block configurations, identifying opportunities for improvement.
• Perform static timing analysis (STA), investigate setup and hold timing violations, and support timing closure activities.
• Execute physical verification checks, including DRC, LVS, and IR-drop analysis, and assist with resolving design issues.
• Leverage Generative AI, AI Assistants, and Agentic AI solutions to automate data collection, reporting, comparison, and workflow optimization for PPA analysis.

Skills

Python scripting

Problem solving

Debugging

VLSI concepts

Education

B.S. or M.S. in Electrical/Computer Engineering or related field

Tools

Synopsys ICC2

Cadence Innovus

PrimeTime

Job description

Micron Technology is seeking a DTCO Intern to gain hands‑on experience optimizing power, performance, and area for memory products. You will work on standard cell logic, use industry tools for floorplanning, CTS, placement, routing, and timing closure, and analyze PPA across libraries and configurations.

You will apply AI-assisted methods to automate data collection, reporting, and workflow optimization while developing skills in physical design and timing analysis.