DTCO Intern: PPA Optimization in Physical Design

1000 Micron Technology, Inc.; Boise (ID); On-site; USD 28,000 - 41,000; Full time

Job summary

Micron Technology, Inc. is seeking a DTCO Intern in Boise to gain hands-on experience optimizing power, performance, and area at the standard cell and logic block level. You will use industry-standard placement and routing tools to assess PPA and contribute to design analysis, timing closure, and AI-enabled automation.

The role requires pursuing a B.S. or M.S. in EE/CE, understanding VLSI concepts, and experience with Python, Perl, or TCL.

Qualifications

• Demonstrated understanding of VLSI design concepts, CMOS circuits, digital logic, and the ASIC physical design flow.
• Experience with scripting languages (Python, Perl, TCL) from coursework or projects.
• Strong analytical, problem-solving, and debugging skills with attention to detail.

Responsibilities

• Implement standard cell logic blocks using industry-standard physical design tools, including floorplanning, placement, CTS, routing, and optimization focused on PPA.
• Analyze and benchmark power, performance, and area across standard cell libraries and logic block configurations to identify opportunities for improvement.
• Perform static timing analysis (STA), investigate setup and hold timing violations, and support timing closure activities.
• Execute physical verification checks (DRC, LVS, IR-drop) and assist in resolving design issues.
• Leverage AI, Generative AI, LLMs, or AI-assisted coding to automate data collection, reporting, and workflow optimization for PPA analysis.

Skills

VLSI design concepts

CMOS circuits

Digital logic

ASIC physical design flow

Python

Perl

TCL

Analytical/problem-solving

Education

B.S. or M.S. in Electrical Engineering or Computer Engineering

Tools

Synopsys ICC2

Cadence Innovus

PrimeTime

Job description

Micron Technology, Inc. is seeking a DTCO Intern in Boise to gain hands-on experience optimizing power, performance, and area at the standard cell and logic block level. You will use industry-standard placement and routing tools to assess PPA and contribute to design analysis, timing closure, and AI-enabled automation.

The role requires pursuing a B.S. or M.S. in EE/CE, understanding VLSI concepts, and experience with Python, Perl, or TCL.